Simplified buried plate structure and process for...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE21396, C257SE21653, C257SE27112

Reexamination Certificate

active

08053823

ABSTRACT:
A structure is provided herein which includes an array of trench capacitors having at least portions disposed below a buried oxide layer of an SOI substrate. Each trench capacitor shares a common unitary buried capacitor plate which includes at least a portion of a first unitary semiconductor region disposed below the buried oxide layer. An upper boundary of the buried capacitor plate defines a plane parallel to a major surface of the substrate which extends laterally throughout the array of trench capacitors. In a particular embodiment, which starts from either an SOI or a bulk substrate, trenches of the array and a contact hole are formed simultaneously, such that the contact hole extends to substantially the same depth as the trenches. The contact hole preferably has substantially greater width than the trenches such that the conductive contact via can be formed simultaneously by processing used to form trench capacitors extending along walls of the trenches.

REFERENCES:
patent: 5661320 (1997-08-01), Moriya
patent: 6552381 (2003-04-01), Chittipeddi et al.
patent: 6635915 (2003-10-01), Kokubun
patent: 7015526 (2006-03-01), Bonart
patent: 2004/0036097 (2004-02-01), Ping et al.
patent: 2004/0135187 (2004-07-01), Bonart
patent: 2005/0260859 (2005-11-01), Deshpande et al.

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