Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-07-07
2004-10-12
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S706000
Reexamination Certificate
active
06803267
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to organic memory devices and, in particular, to patterning organic memory devices.
BACKGROUND OF THE INVENTION
The volume, use and complexity of computers and electronic devices are persistently increasing. As computers continually become more powerful, new and improved electronic devices are continuously developed (e.g., digital audio players, video players). Additionally, the growth and use of digital media (e.g., digital audio, video, images, and the like) have further pushed development of these devices. This growth and development has vastly increased the amount of information desired/required to be stored and maintained for computer and electronic devices.
Memory devices generally include arrays of memory cells. Each memory cell can be accessed or “read”, “written”, and “erased” with information. The memory cells maintain information in an “off” or an “on” state (e.g., are limited to 2 states), also referred to as “0” and “1”. Typically, a memory device is addressed to retrieve a specified number of byte(s) (e.g., 8 memory cells per byte). For volatile memory devices, the memory cells must be periodically “refreshed” in order to maintain their state. Such memory devices are usually fabricated from semiconductor devices that perform these various functions and are capable of switching and maintaining the two states. The devices are often fabricated with inorganic solid state technology, such as, crystalline silicon devices. A common semiconductor device employed in memory devices is the metal oxide semiconductor field effect transistor (MOSFET).
Because of the increasing demand for information storage, memory device developers and manufacturers are constantly attempting to increase storage capacity for memory devices (e.g., increase storage per die or chip). A postage-stamp-sized piece of silicon may contain tens of millions of transistors, each transistor as small as a few hundred nanometers. However, silicon-based devices are approaching their fundamental physical size limits. Inorganic solid-state devices are generally encumbered with a complex architecture which leads to high cost and a loss of data storage density. The volatile semiconductor memories based on inorganic semiconductor material must constantly be supplied with electric current with a resulting heating and high electric power consumption in order to maintain stored information. Non-volatile semiconductor devices have a reduced data rate and relatively high power consumption and large degree of complexity.
Moreover, as the size of inorganic solid-state devices decreases and integration increases, sensitivity to alignment tolerances increases making fabrication markedly more difficult. Formation of features at small minimum sizes does not imply that the minimum size can be used for fabrication of working circuits. It is necessary to have alignment tolerances, which are much smaller than the small minimum size, for example, one quarter the minimum size.
Scaling inorganic solid-state devices raises issues with dopant diffusion lengths. As dimensions are reduced, the dopant diffusion lengths in silicon are posing difficulties in process design. In this connection, many accommodations are made to reduce dopant mobility and to reduce time at high temperatures. However, it is not clear that such accommodations can be continued indefinitely. Furthermore, applying a voltage across a semiconductor junction (in the reverse-bias direction) creates a depletion region around the junction. The width of the depletion region depends on the doping levels of the semiconductor. If the depletion region spreads to contact another depletion region, punch-through or uncontrolled current flow, may occur.
Higher doping levels tend to minimize the separations required to prevent punch-through. However, if the voltage change per unit distance is large, further difficulties are created in that a large voltage change per unit distance implies that the magnitude of the electric field is large. An electron traversing such a sharp gradient may be accelerated to an energy level significantly higher than the minimum conduction band energy. Such an electron is known as a hot electron, and may be sufficiently energetic to pass through an insulator, leading to irreversibly degradation of a semiconductor device.
Scaling and integration makes isolation in a monolithic semiconductor substrate more challenging. In particular, lateral isolation of devices from each other is difficult in some situations. Another difficulty is leakage current scaling. Yet another difficulty is presented by the diffusion of carriers within the substrate; that is free carriers can diffuse over many tens of microns and neutralize a stored charge. Thus, further device shrinking and density increasing may be limited for inorganic memory devices. Furthermore, such device shrinkage for inorganic non-volatile memory devices while meeting increased performance demands is particularly difficult, especially while maintaining low costs.
SUMMARY OF THE INVENTION
The following is a summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not intended to identify key/critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to systems and methods for fabricating an organic memory element and/or device wherein a silicon-based resist is employed to mitigate difficulties with pattering a carbon resist deposited over an organic semiconductor. Typically, a carbon resist is employed, and is adequate when utilized in conjunction with a silicon substrate, for example. However, patterning can be difficult when both the resist and the organic semiconductor are carbon-based because patterning techniques are not carbon selective.
The present invention mitigates issues associated with utilizing a carbon resist with an organic semiconductor, including the difficulties described above, by employing a silicon-based resist. Thus the present invention affords one or more methods to improve patterning and mitigates problems associated with employing a carbon resist with a carbon organic semiconductor.
The fabrication methods include forming an organic semiconductor as a layer and/or within a via in a layer, and subsequently depositing a silicon-based resist over the organic semiconductor layer wherein the silicon-based resist is then patterned utilizing a positive and/or negative resist technique. The fabrication methods can be employed to form one or more memory elements, serially and/or concurrently.
A formed organic semiconductor memory element can be employed as a memory cell, or a storage unit, to store information within a memory structure. Generally, a memory structure includes one or more electrodes (e.g., a top and a bottom electrode), a memory element and a passive material associated with at least one electrode. Information can be read, written and/or erased from the memory element by applying a suitable electrical potential across the memory structure (e.g., across electrodes).
In addition to a single cell memory structure, the methods described herein can be utilized to construct a multi-celled memory structure. In an aspect of the present invention, multiple memory elements can be formed within a structure, wherein the formation of the memory elements occurs serially and/or concurrently. In another aspect of the present invention, multiple structures (each structure with one or more memory elements) can be coupled through a component to facilitate programming and/or form an isolation barrier between memory structures.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustr
Buynoski Matthew S.
Cheung Patrick K.
Hui Angela T.
Khathuria Ashok M.
Lopatin Sergey D.
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Le Thao P.
Nelms David
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