Silicon carbide cap layers for low dielectric constant...

Details Silicon carbide cap layers for low dielectric constant... Silicon carbide cap layers for low dielectric constant...

2001-03-28

2002-10-29

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

C438S756000, C438S780000, C438S783000, C257S689000, C257S750000

Reexamination Certificate

active

06472333

ABSTRACT:

BACKGROUND OF THE DISCLOSURE
1. Field of the Invention
The present invention relates to silicon carbide layers and, more particularly to their use in integrated circuit fabrication processes.
2. Description of the Background Art
Integrated circuits have evolved into complex devices that can include millions of components (e. g., transistors, capacitors, and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e. g., sub-micron dimensions), the materials used to fabricate such components contribute to their electrical performance. For example, low resistivity metal interconnects (e. g., copper (Cu) and aluminum (Al)) provide conductive paths between the components on integrated circuits. Typically, the metal interconnects are electrically isolated from each other by an insulating material. When the distance between adjacent metal interconnects and/or the thickness of the insulating material has sub-micron dimensions, capacitive coupling potentially occurs between such interconnects. Capacitive coupling between adjacent metal interconnects may cause cross-talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the integrated circuit.
In order to minimize capacitive coupling between adjacent metal interconnects, low dielectric constant bulk insulating materials (e. g., dielectric constants less than about 3.0) are needed. Examples of low dielectric constant bulk insulating materials include organosilicates, silicon oxides, and fluorosilicate glass (FSG), among others.
Typically, some bulk insulating materials are deposited using low temperature chemical vapor deposition (CVD) or spin-on processes. These bulk insulating material layers may have poor mechanical strength (e. g., hardness of less than about 0.3 GPa (gigapascals)).
Post-deposition annealing processes may be used to improve the mechanical strength of such bulk insulating material layers. Cap layers comprising an oxide or silicon nitride (SiN) material may be deposited on the bulk insulating material layers prior to annealing to protect the bulk insulating material layer from being scratched when the semiconductor wafer is moved between process chambers. However, oxide or silicon nitride cap layers are impermeable to outgassing of carbon, hydrogen and/or oxygen species from the bulk insulating material, causing such cap layers to undesirably bubble and/or crack during the annealing process.
Therefore, a need exists for cap layers for use on low dielectric constant bulk insulating material annealing processes.
SUMMARY OF THE INVENTION
A method of forming a low dielectric constant silicate material for use in integrated circuit fabrication processes is provided. The low dielectric constant silicate material is formed by reacting by reacting a gas mixture comprising an organosilane compound, an oxygen source, and an inert gas. Thereafter, a silicon carbide cap layer is formed on the silicate material by reacting a gas mixture comprising a silicon source and a carbon source. The silicon carbide cap layer protects the underlying organosilicate layer from cracking and peeling when it is hardened during a subsequent annealing step.
The low dielectric constant silicate layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the low dielectric silicate layer is incorporated into a damascene structure. For such an embodiment, a preferred process sequence includes depositing a barrier layer on a substrate. A first low dielectric constant silicate layer along with a first silicon carbide cap layer are formed on the barrier layer. Thereafter, a second low dielectric constant silicate layer as well as a second silicon carbide cap layer are formed on the first silicate layer and first silicon carbide cap layer. The second silicon carbide cap layer is patterned to define vias therethrough. After the vias are defined through the second silicon carbide cap layer, such pattern is transferred through the second low dielectric constant silicate layer as well as the first silicon carbide cap layer using the second silicon carbide cap layer as a hard mask. Thereafter, the second silicon carbide layer is patterned to define interconnects therethrough. The interconnects formed in the second silicon carbide cap layer are positioned over the vias previously formed therethrough. After the interconnect pattern is defined through the second silicon carbide cap layer, the interconnect pattern is transferred through the second low dielectric constant silicate layer, while simultaneously transferring the via pattern through the first low dielectric constant silicate layer. The damascene structure is completed by filling the interconnects and vias with a conductive material.


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