Silicide gate transistors and method of manufacture

Details Silicide gate transistors and method of manufacture Silicide gate transistors and method of manufacture

2006-06-27

2006-06-27

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S592000, C438S595000

Reexamination Certificate

active

07067379

ABSTRACT:
A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.

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B. Tavel et al., “Totally Silicided (CoSi2) Polysilican: a novel approach to very low-resistive gate without metal cmp nor etching,” pub. at the Int'l Electron Device Meeting (IEDM), Washington, DC. , 2001, pp. 825-828.

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