Sidewall coverage for copper damascene filling

Details Sidewall coverage for copper damascene filling Sidewall coverage for copper damascene filling

2007-10-16

2007-10-16

Ahmed, Shamim (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S675000, C438S686000, C204S192120

Reexamination Certificate

active

10733722

ABSTRACT:
A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

REFERENCES:
patent: 5296407 (1994-03-01), Eguchi
patent: 5316974 (1994-05-01), Crank
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5677244 (1997-10-01), Venkatraman
patent: 5814557 (1998-09-01), Venkatraman et al.
patent: 6686280 (2004-02-01), Shue et al.
patent: 2002/0058409 (2002-05-01), Lin et al.

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