Short circuited capacitor detection in AC coupled links...

Details Short circuited capacitor detection in AC coupled links... Short circuited capacitor detection in AC coupled links...

2001-10-31

2004-11-02

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000

Reexamination Certificate

active

06813737

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to boundary scan testing of interconnections between integrated circuits. More particularly, the present invention relates to AC coupled boundary scan testing.
BACKGROUND OF THE INVENTION
Electronic systems generally include at least one printed circuit board (PCB) containing one or more integrated circuits (ICs). ICs typically include input/output (I/O) pins which may be coupled to various interconnects of the PCB. Testing performance of electronic systems which include PCBs and ICs typically requires testing at multiple levels including the chip level, the board level, and the system level. Testing at the board level includes testing interconnects of the PCB. Testing at the system level requires analysis of interconnections between and among the ICs, the PCBs, and other devices both on and off the PCB.
To enhance testability at the board level as well as at the system level, a common design practice at the chip level is to incorporate boundary scan test logic into an IC in accordance with Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1, Standard Test Access Port and Boundary-Scan Architecture. IEEE Standard 1149.1 specifies the function of JTAG logic, which is named for the Joint Test Action Group, for control of boundary scan testing. The two basic elements of an IC are its core logic and its I/O pins. In accordance with IEEE Standard 1149.1, boundary scan cells (BSCs) are inserted between the core logic and the I/O pins of the IC. BSCs are typically inserted for all I/O pins of the plurality of ICs on the PCB and may be used to test the integrity of the interconnections between the plurality of ICs.
Each IC may be controlled by boundary scan logic, in accordance with IEEE Standard 1149.1, to operate either in a system mode or in a JTAG test mode. In the system mode, system data signals relating to core functions of the IC are passed through the I/O pins to and from devices external to the IC. In the JTAG test mode, test data are provided by a boundary scan chain for the purpose of testing interconnections between the IC and devices external to the IC. A boundary scan chain is formed when the ICs are connected in a serial daisy chain. The boundary scan logic also provides conventional test control signals which include mode signals, shift signals, clock signals, and update signals, among others. The shift control signal instructions include a bypass instruction, a sample instruction, and a cross test instruction. The cross test instruction controls BSCs to perform a boundary scan test among the various ICs.
The IC further includes a test data input (TDI) demultiplexer, a test data output (TDO) multiplexer, a bypass register, an instruction register, an identification register, and a test access port (TAP) controller. The TDI demultiplexer includes an input coupled to receive a test data signal from the boundary scan logic which is typically external to the IC. The TDI demultiplexer includes a first output coupled to a TDI input of a first BSC of the plurality of BSCs in the IC. Each of the BSCs includes a TDI input and a TDO output. Each of BSCs is connected serially from a TDO output to a TDI input to propagate test data signals from one BSC to the next BSC in the chain. The TDI demultiplexer further includes a second output coupled to an input of the core logic, a third output coupled to an input of the bypass register; a fourth output coupled to an input of the instruction register; and a fifth output coupled to an input of the identification register.
The TDO multiplexer includes an output which is coupled to provide a test data signal to another IC or to the boundary scan logic. The TDO multiplexer further includes: a first input coupled to a TDO output of a last BSC of the plurality of BSCs in the IC, a second input coupled to an output of the core logic; a third input coupled to an output of the bypass register; a fourth input coupled to an output of the instruction register, and a fifth input coupled to an output of the identification register. The identification register includes inputs coupled to outputs of the TAP controller. The TAP controller includes inputs coupled to receive a Test Mode Select (TMS) signal, a Test Clock (TCK) signal, and a Test Reset (TRST) signal from the boundary scan logic.
In general, there are three possible I/O structures for an IC. These are a two-state I/O structure, a three-state I/O structure, and a bi-directional I/O structure. Each of the three I/O structures provides coupling between the core logic and at least one I/O pin. Any or all of the I/O structures may be used in an IC depending on the particular circumstances. The two-state I/O structure includes a two-state output buffer having a data input and a data output. The input of the two-state output buffer is coupled to a system data output of the core logic. The output of the two-state output buffer is coupled to an I/O pin. The three-state I/O structure includes a three-state output buffer having a data input, a data output, and a control input. The data input of the three-state output buffer is coupled to a system data output of the core logic. The data output of the three-state output buffer is coupled to an I/O pin. The control input of the three-state output buffer is coupled to a three-state system control signal output line of the core logic. The bi-directional I/O structure includes a bi-directional buffer. The bidirectional buffer includes an output buffer element having a data input a data output, and a control input and an in put buffer element having a data input and a data output. The control input of the output buffer element is coupled to a bidirectional control signal output line of the core logic. The data input of the output buffer element is coupled to a system data output of the core logic. The data output of the input buffer element is coupled to a system data received input of the core logic. The data output of the output buffer element and the data input of the input buffer element are coupled together at an I/O pin.
According to conventional methods and apparatus for boundary scan testing, the BSCs are inserted into the I/O structures between the buffers and the core logic. For a two-state output structure, a BSC is inserted between the core logic and the data input of the two-state output buffer. For a three-state output structure, a BSC is inserted between the system data output of the core logic and the data input of the three-state output buffer. Also, a BSC is inserted between the three-state control signal output line of the core logic and the control input of the three-state output buffer. For a bi-directional output structure, a BSC is inserted between the system control signal output line of the core logic and the bi-directional output buffer. Also, a bi-directional BSC is inserted between the core logic and the bi-directional output buffer.
Turning first to
FIG. 1
, a detailed logic block diagram of a prior art BSC
100
is shown. The BSC
100
includes a boundary scan mode multiplexer (mode multiplexer)
112
, a shift multiplexer
114
, a data shift/capture register
116
, and an update data register
118
. The mode multiplexer
112
and the shift multiplexer
114
each have a system input (
0
), an update input (
1
), an output
120
,
122
, and a select line
124
,
126
. The data shift/capture register
116
and the update data register
118
each have a data input (D), a clock input (CLK), a normal output (Q), and an inverted output (Q bar).
The BSC
100
includes a system data input. (SDI) line
128
for receiving system signals including system data signals and system control signals from the system signal output lines, including the system data signal output lines and the system control signal output lines, of the core logic (not shown). If the BSC
100
is used for control purposes, the SDI line
128
may receive a system control signal from the core logic. If the BSC
100
is used for output, the SDI line
128
may receive a system data signal from the c

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