Serializer/deserializer circuit for jitter sensitivity...

Details Serializer/deserializer circuit for jitter sensitivity... Serializer/deserializer circuit for jitter sensitivity...

2007-07-31

2007-07-31

Lamarre, Guy (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S744000, C714S738000, C324S073100

Reexamination Certificate

active

10707961

ABSTRACT:
Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

REFERENCES:
patent: 5790563 (1998-08-01), Ramamurthy et al.
patent: 6215835 (2001-04-01), Kyles
patent: 6658363 (2003-12-01), Mejia et al.
patent: 6725408 (2004-04-01), Cao et al.
patent: 6865222 (2005-03-01), Payne

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