Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1994-04-07
1995-06-06
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36518912, 365221, 365240, G11C 700
Patent
active
054228492
ABSTRACT:
A serial data port in a dual port memory device adapted to receive incoming serial data and transfer the incoming serial data to a general data register, comprising; a plurality of data latches storing a portion of the incoming serial data, each data latch comprising a plurality of shift registers, and each shift register being responsive to one of a plurality of sequentially generated shift register control signals, and a plurality of transfer gates, each transfer gate gating the incoming serial data into a corresponding data latch in responsive to a one of a plurality of sequentially generated data latch control signals, wherein each data latch control signal defines a time period, and the plurality of shift register control signals is sequentially generated within the time period.
REFERENCES:
patent: 4799198 (1989-01-01), Ogawa
patent: 4912680 (1990-03-01), Masaki et al.
patent: 4987559 (1991-01-01), Miyauchi et al.
patent: 5195055 (1993-03-01), Mizuoka et al.
patent: 5343439 (1994-08-01), Hoshino
Donohoe Charles R.
Nguyen Tan
Popek Joseph A.
Samsung Electronics Co,. Ltd.
Whitt Stephen R.
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