Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-06-29
2004-06-22
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C713S600000, C714S734000
Reexamination Certificate
active
06754868
ABSTRACT:
FIELD
The present invention relates generally to a system for testing integrated circuits (ICs), and, more particularly, to a method and apparatus for high speed testing of ICs having either logic circuits, memory arrays or both.
BACKGROUND
Manufacturers in the electronic industry use test systems to automatically test various electronic components and integrated circuits (ICs) to weed out defective devices or ICs. Broadly, there are two types of test systems, those suitable for testing memory arrays or circuits, such as flash memory or Random Access Memories (RAM), those suitable for testing logic circuits, such as Micro Controllers, Application Specific ICs (ASICs), and Programmable Logic Devices (PLDs). Generally, it is desirable to test the ICs at several points during the manufacturing process including while they are still part of a wafer or substrate and after packaging the devices before they are mounted or assembled on modules, cards or boards. This repetitive testing imposes demands on test systems to automatically perform tests at high speed and with a high degree of accuracy. Moreover, the trend in the electronic industry has been to further increase the miniaturization of electronic devices and circuits, thereby allowing for an increase in the complexity of the IC. Thus, as ICs become more complex, the complexity of the test systems must increase correspondingly.
An example of part of a prior art logic test system
10
for testing logic circuits in an IC, commonly known as a Device Under Test or DUT
12
having a number of pins
14
is shown in FIG.
1
. Referring to
FIG. 1
, test system
10
typically includes a general purpose computer
16
or PC, a clock
18
, logic vector memory (LVM
20
) with a sequencer, a number of timing and format circuits (T/Fs
22
), and a number of pin electronics or P/E channels
24
. Computer
16
loads test programs and controls operation of other components of test system
10
. Clock
18
generates system clocks and the test system period, which are provided to LVM
20
, T/Fs
22
, and other pipeline circuits in the test system. LVM
20
stores and sequences test signals, commonly known as test vectors, used during the testing process. T/Fs
22
adjust the timing and formatting of various signals, i.e., data, strobe and input/output (I/O) control signals, received from LVM
20
and couple the LVM to DUT
12
, through PE channels
24
. It should be noted that although test system
10
may include a single computer
16
, clock
18
and LVM
20
, it generally includes one T/F
22
and an associated P/E channel
24
for each pin
14
on a DUT
12
, shown here as having pins
1
through n.
PE channels
24
typically include a PE driver
26
for applying a test vector, data, to a pin
14
of DUT
12
, a comparator
28
for comparing a DUT output signal with an expected output signal, and an error logic circuit
30
for coupling results of the comparison back to error processing circuitry and and an error capture memory (not shown). Generally, PE driver
26
and comparator
28
are not active in the same PE channels
24
at the same time, since pin
14
is either receiving data or control signals or transmitting a result at a given time. PE channels
24
further include a data line
32
for coupling the test vectors from T/F
22
to PE driver
26
and error logic
30
, an enable or control line
34
for enabling the PE driver to apply the test vector to DUT
12
, and a strobe line
36
for enabling error logic
30
.
An example of part of a prior art memory test system for testing memory arrays in DUTs is shown in FIG.
2
. Referring to
FIG. 2
, the test system
38
typically includes a computer
40
, a clock
42
, an algorithmic pattern generator (APG
44
), T/Fs
46
, and P/E channels
48
,
49
,
50
. APG
44
is used for generating a test signal or test vector for testing the memory array in the DUT. As above, it is to be noted that test system
38
further includes a single computer
40
, clock
42
and APG
44
, but a number of T/F
46
with associated P/E channel
48
,
49
,
50
for each pin on a DUT (not shown). For purposes of clarity,
FIG. 2
illustrates only three T/Fs
46
and PE channels
48
,
49
,
50
. PE channel
48
and PE channel
49
differ from PE channel
50
because they merely provide address and clock signals to the DUT and therefore require only a PE driver
52
. PE channel
50
both provides data to and receives data from a pin on the DUT, and therefore includes, in addition to PE driver
52
, a comparator
54
, an error logic circuit
56
that functions as described above. PE driver
52
is coupled to T/F
46
by data line
58
and control line
60
. Comparator
54
and error logic
56
are coupled to T/F
46
by strobe line
62
and data line
58
.
A fundamental problem with the above test systems
10
,
38
is their inability to easily test in parallel DUTs having a combination of both logic circuits and memory arrays.
Another problem with the above test systems
10
,
38
, is their inability to switch the pattern source signal coupled to the pin at least twice in each DUT cycle.
Yet another problem with the above test systems
10
,
38
, is their difficulty in testing DUTs having serial data paths.
Still another problem with the memory test system
38
described above, is the inability to route any output from the APG
44
to any PE channel
48
,
49
,
50
, and therefore to any pin on the DUT. For example, in a test system
38
designed to accommodate 64 pin ICs, outputs from an address T/F may be mapped to any one address of address pins one through twenty-four, while outputs from a data T/F would be mapped to data pins twenty-five through fifty-six, and outputs from a clock T/F are mapped to pins fifty-seven through sixty-four. Thus, it is difficult if not impossible to reconfigure the test system
38
to accommodate DUTs having a different number of pins and/or arranged in a different configuration.
SUMMARY
The present invention is directed to an apparatus and method for high speed testing of integrated circuits (ICs) having either logic circuits, memory arrays or both.
In one aspect, the present invention is directed to an apparatus for testing a device under test (DUT). Generally, the apparatus includes: (i) a pattern generator having a number of outputs for outputting signals for testing the DUT; (ii) a number of pin electronics channels (P/Es) each coupling to one of a number of pins on the DUT; (iii) a number of timing and format circuits (T/Fs) for mapping signals to at least one of the P/Es; (iv) a pin scrambling circuit connected between the pattern generator and the T/Fs, the pin scrambling circuit capable of mapping at least two signals from any of the pattern generator outputs to any one of the T/Fs; and (v) a clock for providing a clock signal having a clock cycle to the pattern generator and the T/Fs. Preferably, the T/Fs are capable of switching the signals coupled to the P/Es at least twice in a clock cycle.
In one embodiment, the pattern generator includes logic vector memory (LVM) for testing logic circuits, and a memory signal source, such as an algorithmic pattern generator (APG), for testing memory arrays, and the scrambling circuit is capable of mapping signals from the LVM and the APG to separate T/Fs, thereby enabling the apparatus to simultaneously test one or more DUTs having logic circuits, memory arrays or both. Alternatively or additionally, the pattern generator can include a scan memory for serial type test interfaces or structural test.
In another embodiment, the pin scrambling circuit is capable of sequentially coupling signals on a number of the pattern generator outputs, generated in parallel, to one of the P/Es to test a DUT having a serial input. In one version of this embodiment, the pin scrambling circuit is capable of simultaneously coupling a number of signals to other pins on the DUT to simultaneously test DUTs having both serial and parallel inputs, such as for example NAND flash memories.
In another embodiment, a number of the apparatuses are capable of bei
Bristow Steven R.
Craighead Seth W.
Magliocco Paul
Dorsey & Whitney LLP
Nextest Systems Corporation
Tu Christine T.
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