Semiconductor test system and method for effectively testing...

Details Semiconductor test system and method for effectively testing... Semiconductor test system and method for effectively testing...

2006-09-26

2006-09-26

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

07114108

ABSTRACT:
A semiconductor device having many pins is tested using a test system having fewer pins. The test system includes a pin electronics (PE) card and a pattern memory. The PE card preferably includes a plurality of comparator and driver units to drive predetermined input signal pattern to be applied to an input pin of the semiconductor device and to compare data output from an output pin of the semiconductor device with a predetermined output signal pattern. Some or all of the pins of the semiconductor device may be divided into pin groups having K number of pins. The PE card also preferably includes a plurality of control units for electrically connecting each of the comparator and driver units to a selected pin in a selected pin group in response to a control signal.

REFERENCES:
patent: 4746855 (1988-05-01), Wrinn
patent: 4775977 (1988-10-01), Dehara
patent: 5701306 (1997-12-01), Arai
patent: 5794175 (1998-08-01), Conner
patent: 6157200 (2000-12-01), Okayasu
patent: 9091998 (1998-02-01), None
patent: 11190761 (1999-07-01), None
patent: P1998-032494 (1998-07-01), None
English Abstract of JP 9091998.
English Abstract of P1998-032494.

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