Semiconductor test device and timing measurement method

Details Semiconductor test device and timing measurement method Semiconductor test device and timing measurement method

2007-03-27

2007-03-27

Britt, Cynthia (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S700000, C714S798000

Reexamination Certificate

active

10936392

ABSTRACT:
A semiconductor test equipment and a timing measuring method for use in the semiconductor test equipment are provided, that can perform simultaneous measurement of timings of defined times between edges in cycles even in a case where a capacity is large as in a test pattern for the semiconductor test equipment or a case where the cycles are away from each other. In order to achieve this, the semiconductor test equipment includes: a data shifting flip-flip for shifting input data with a reference clock of the semiconductor test equipment by a period of one clock, provided in a secondary logical comparison circuit71; the first logical comparison and selection circuit71afor determining whether timings of the first defined time Ta that is a period between two pre-selected edges are good or not, and outputting a determination result; and the second logical comparison and selection circuit71bfor determining whether timings of the second defined time Tb that is a period between two pre-selected edges are good or not, and outputting a determination result.

REFERENCES:
patent: 6282680 (2001-08-01), Takagi et al.
patent: 7010729 (2006-03-01), Doi et al.
patent: 4-259869 (1992-09-01), None
Patent Abstracts of Japan, publication No. 04-259869, publication date Sep. 16, 1992 (1 page).
Advantest Corp., “Handotai Shiken Sochi ni Okeru Cycle-Kan no Sokutei”, Japan Institute of Invention and Innovation (JIII), Journal of Tecnical Disclosure, (Jul. 16, 2001), 2001-4056, full text.
International Search Report dated Jun. 17, 2003 (2 pages).

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