Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-07-01
2003-07-01
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C365S201000
Reexamination Certificate
active
06587975
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test method for effectively performing a test on a semiconductor memory which requires rewriting of data or a semiconductor memory which is provided with some error memory cells but regarded as acceptable since the number of normal memory cells is not less than a predetermined number (hereinafter referred to as “MGM (Mostly Good Memory)”). The present invention also relates to an semiconductor test apparatus which comprises circuits for the above test method.
2. Description of the Background Art
<Characteristics of Flash Memory>
A flash memory is one of so-called nonvolatile memories which hold stored data even if power is lost. It is capable of electrically erasing the stored data.
The flash memory stores either “0” or “1” in each memory cell by varying the threshold values of those cells. Erasing such data is performed not by one erase operation but by repetitions of the operation to gradually lower the threshold value. Since there is a restriction on the number of times the erase operation can be repeated (hereinafter referred to as “the number of retries”), it is necessary in the erase test to check whether all cells have been erased within a predetermined limitation of times or not. The principle and operating mechanism of an NOR type flash memory are, for example, disclosed in Mitsubishi Semiconductor Data Book 1997, Mitsubishi Application Note, p4-8-p4-15 issued by the semiconductor business planning department of Mitsubishi Electric Corporation (prior art reference (1)).
To erase data stored in the NOR type flash memory, a method for erasing data by one operation is employed. This is not to erase data of a specific cell but to erase all cells in the memory. Thus, it is necessary not only to check at each address of the memory whether the erasing has been completed or not, but also to check the total number of erase retries during test irrespective of the addresses. The procedure (hereinafter referred to as “test flow”) of the erase test is, for example, disclosed in Mitsubishi Semiconductor Data Book 1997, Mitsubishi Application Note, p4-18, 19 (prior art reference (2)). Similarly, a write test flow is disclosed in Mitsubishi Semiconductor Data Book 1997, Mitsubishi Application Note, p4-16, 17 (prior art reference (3)).
<Conventional Test Apparatus and Method>
Conventional circuitry for the flash memory test is approximately configured as shown in
FIGS. 34 and 35
, which includes a test pattern generating portion and a controller portion for controlling write and erase retry operations. In the structure of
FIGS. 34 and 35
, there are two memories under test
8
(
8
a,
8
b
).
FIG. 47
shows connection between
FIGS. 34 and 35
.
A semiconductor test apparatus comprises a clock generator
6
for generating a periodic clock signal
1
which is test periodic timing, a synchronizing clock signal
2
for synchronization with signals, a delay clock signal
3
for delaying signals, an event clock signal
4
which is timing of test pattern changes, and a strobe signal
5
which is judgement timing; an instruction memory
7
for storing a program which describes test patterns generated during operation; and an address generator
10
for decoding the program from the instruction memory
7
and generating address patterns
9
(
9
a,
9
b
) to have access to the memories under test
8
(
8
a,
8
b
).
The semiconductor test apparatus further comprises a data generator
14
for decoding the program from the instruction memory
7
and generating data patterns
11
(
11
a,
11
b
) to be applied to the memories under test
8
and data patterns
13
(
13
a,
13
b
) to be compared with data
12
(
12
a,
12
b
) from the memories under test
8
; control signal generators
16
(
16
a,
16
b
) for generating control patterns
15
(
15
a,
15
b
) to be applied to the memories under test
8
; and a program counter
18
for generating an address
17
to have access to the instruction memory
7
.
In addition, the semiconductor test apparatus comprises signal waveform forming circuits
20
(
20
a,
20
b
) for generating input signals
19
(
19
a,
19
b
) to be applied to the memories under test
8
with timings of the event clock signal
4
from the clock generator
6
and various patterns from the address generator
10
; the data generator
14
; and the control signal generators
16
(
16
a,
16
b
).
The test apparatus is further provided with judging circuits
25
for comparing the output data
12
from the memories under test
8
with the data patterns
13
from the data generator
14
with timing of the strobe signal
5
from the clock generator
6
, applying error signals
21
(
21
a,
21
b
) and
22
(
22
a,
22
b
), or comparison result, to a match controller portion
23
P, and canceling the error signals
21
,
22
on receipt of reset signals
24
(
24
a,
24
b
) from the match controller portion
23
P. On receipt of a match control signal
26
from the instruction memory
7
, the match controller portion
23
P performs retry operations in synchronization with the clocks signals
1
,
2
. Signals
27
through
31
will be described later with reference to
FIGS. 36 and 37
.
FIGS. 36 and 37
show the circuit configuration of the match controller portion
23
P. As a matter of convenience, some of external input signals in
FIGS. 36 and 37
are not shown in
FIGS. 34 and 35
, but they exist in practice.
FIG. 48
shows connection between
FIGS. 36 and 37
.
A periodic delay circuit
33
in the match controller portion
23
P is composed of a D flip-flop
501
and an AND gate
502
. It generates a control delay clock signal
32
by delaying the match control signal
26
for a single one period by the periodic clock signal
1
as shown in
FIG. 41. A
pipeline circuit
34
receives the output signal
32
of the periodic delay circuit
33
and outputs a signal
35
, which is delayed with the synchronizing clock signal
2
as a trigger, to one input of an AND gate
503
. Receiving the synchronizing clock signal
2
at its other input, the AND gate
503
outputs a signal
36
which is pulse-converted by the synchronizing clock signal
2
. For reference, a correlation between the control delay clock signal
32
and the signal
36
is shown in FIG.
42
. The match controller portion
23
P operates in synchronization with this signal
36
, so that match control by the match controller portion
23
P is enabled after a delay of a single period.
A clock stop latch circuit
45
(
45
a,
45
b
) receives at its set input S the output of an AND gate
508
(
508
a,
508
b
) which receives the error signal
21
(
21
a,
21
b
) and the signal
36
. If the error signal
21
is “1 (pass)”, the circuit
45
sets a temporary clock stop signal
37
(
37
a,
37
b
) to “1” and a signal
38
(
38
a,
38
b
), which is to be a switching signal
27
for the execution address
17
indicated by the program counter
18
, to “0”
The clock stop latch circuit
45
further receives at its reset input R an output signal
44
(
44
a,
44
b
) of an AND gate
507
. If a signal
39
and the match control signal
26
are both “1”, a periodic delay circuit
40
(composed of an AND gate
504
, a D flip-flop
505
, and an AND gate
506
) outputs a control delay clock signal
41
which is “1” in synchronization with the periodic clock signal
1
. A signal
43
obtained by delaying the control delay clock signal
41
in a pipeline circuit
42
is given to one input of the AND gate
507
. Since the AND gate
507
receives at its other input the synchronizing clock signal
2
, the signal
43
is pulse-converted by the synchronizing clock signal
2
to be the reset signal
44
(
44
a,
44
b
). By this reset signal
44
, the clock stop latch circuit
45
cancels a temporary clock stop condition.
A loop counter
49
(
49
a,
49
b
) increments the number of retries with the output of an AND gate
510
(
510
a,
510
b
) as a synchronizing signal. The AND gate
510
receives the signal
36
and a signal obtained from the error signal
21
throug
Funakura Teruhiko
Mori Hisaya
De'cady Albert
Mitsubishi Denki & Kabushiki Kaisha
Torres Joseph D.
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