Semiconductor structures and manufacturing methods

Details Semiconductor structures and manufacturing methods Semiconductor structures and manufacturing methods

1999-09-29

2004-05-25

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C438S301000, C438S305000, C438S386000, C257S068000, C257S905000

Reexamination Certificate

active

06740555

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor structures and manufacturing methods and more particularly to the growth of silicon dioxide material on silicon semiconductor bodies with thicknesses substantially independent of the crystallographic orientation of the wall upon which such material is grown.
As is known in the art, many applications require the formation of silicon dioxide material on the walls of a silicon semiconductor body. One such application is in the formation of a gate oxide in a field effect transistor (FET). There, the silicon dioxide is generally thermally grown on the silicon body to provide a gate oxide for the FET. After such formation, a gate stack, i.e., electrode, is formed on the grown silicon dioxide. Next, ions are implanted through the grown silicon dioxide gate material. After activation of the ions by an anneal process, the source and drain regions for the FET are provided.
SUMMARY OF THE INVENTION
In accordance with one feature of the invention, a method is provided for forming substantially uniformly thick, thermally grown, silicon dioxide material on sidewall portions of a trench in a surface of a single crystal semiconductor body independent of crystallographic axis.
In accordance with one embodiment of the invention, a method is provided for forming a thermally grown oxide on a surface having surface portions thereof disposed in different crystallographic planes. The method includes providing a relatively thin material on selected ones of the surface portions, such selected ones of the surface portions having crystallographic planes which, when subjected to a thermal oxidation process, grow such oxide at a relatively higher rate then the rate such oxidation process grows such oxide on un-selected surface portions disposed in other crystallographic planes. The surface portions are subjected to the oxidation process to grow the oxide with a thickness greater than the thickness of the material, such oxide being grown over the selected surface portions and the un-selected surface portions with a substantially uniform thickness.
In one embodiment of the invention, a trench in a surface of a single crystal silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the <
100
> crystallographic plane and another one of such planes being the <
110
> plane. A substantially uniform layer of silicon nitride is formed on the sidewalls of the trench. The trench, with the substantially uniform layer of silicon nitride on the sidewalls thereof, is subjected to a silicon oxidation environment with sidewalls in the <
110
> plane being oxidized at a higher rate than sidewalls in the <
100
> plane producing silicon dioxide on the silicon nitride layer having thickness over the <
110
> plane greater than over the <
100
> plane. The silicon dioxide is subjected to an etch which selectively removes silicon dioxide while leaving substantially un-etched silicon nitride, such subjecting being for a time selected to remove portions of the silicon dioxide over the <
100
> plane to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the <
110
> plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the <
100
> plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the <
110
> plane. The exposed underlying portions of the sidewalls of the trench disposed in the <
100
> plane and the un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the <
110
> plane are subjected to an silicon oxidation environment with the exposed sidewalls in the <
100
> plane being oxidized at substantially the same rate as the sidewalls in the <
110
> plane having the un-etched silicon nitride material thereon to produce a substantially uniform silicon dioxide layer on the sidewalls of the trench.
In accordance with another feature of the invention, a single crystal semiconductor body is provided having a trench with sidewall portions disposed in different crystallographic planes of the body, such sidewall portions having thereon substantially uniformly thick, thermally grown, silicon dioxide material.


REFERENCES:
patent: 3796612 (1974-03-01), Allison
patent: 3883948 (1975-05-01), Allison
patent: 3986200 (1976-10-01), Allison
patent: 4017885 (1977-04-01), Kendall et al.
patent: 4047195 (1977-09-01), Allison
patent: 4278987 (1981-07-01), Imaizumi et al.
patent: 4397075 (1983-08-01), Fatula et al.
patent: 4467343 (1984-08-01), Herberg
patent: 4833516 (1989-05-01), Hwang et al.
patent: 4916511 (1990-04-01), Douglas
patent: 4918503 (1990-04-01), Okuyama
patent: 5307433 (1994-04-01), Stein
patent: 5406515 (1995-04-01), Rajeevakumar
patent: 5484507 (1996-01-01), Ames
patent: 5576223 (1996-11-01), Zeininger et al.
patent: 5641694 (1997-06-01), Kenney
patent: 5744826 (1998-04-01), Takeuchi et al.
patent: RE35810 (1998-05-01), Prall
patent: 5905283 (1999-05-01), Kasai
patent: 6093618 (2000-07-01), Chen et al.
patent: 6140673 (2000-10-01), Kohyama
patent: 6348388 (2002-02-01), Faltermeier et al.
patent: 0 302 204 (1989-02-01), None
Patent Abstracts of Japan Publication No. 63-177546, date of publication of application: Jul. 21, 1988, 1 page. (English Abstract Only).

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