Semiconductor structure useful in a self-aligned contact...

Details Semiconductor structure useful in a self-aligned contact... Semiconductor structure useful in a self-aligned contact...

2001-08-27

2002-08-20

Sherry, Michael (Department: 2829)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

Reexamination Certificate

active

06436844

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor structures and methods of forming semiconductor structures, and, more particularly, to structures and methods of forming structures useful in self-aligned contact etches.
2. Description of Related Art
In the fabrication of multilayered integrated circuits, it is frequently desirable to etch a vertical opening in a layer overlying substrate to form electrical contacts to the substrate. This commonly requires etching through several layers of different types of overlying material. To assure that electrical contact is made with only the substrate, other structures, such as transistor gates, are enclosed in insulating sidewalls and caps that provide a degree of correction or self-alignment to the etch process. One problem in the prior art is that the etching process attacks these insulating surfaces to some extent. If the etch penetrates the insulating surfaces, subsequent deposition of conductive material will short-circuit different layers of the device.
FIGS. 1-4
illustrate various stages of the process in the prior art. The drawings represent vertical sections of the same semiconductor structure
10
.
FIG. 1
shows the structure
10
prior to the contact etch. The goal of the process is to attach a contact to the lower substrate
12
, typically a semiconductor substrate, in a location
13
positioned adjacent two multilayered structures
14
. The multilayered structures
14
can be, for example, comprised of doped polysilicon
16
and silicide
18
. The silicide
18
is typically a tungsten silicide. Both the polysilicon
16
an d silicide
18
are conductive and together may form, for example, a transistor gate. Insulative e layers, such as caps
20
and sidewalls
22
formed of nitride, cover the surfaces and sides of the conducting layers
16
and
18
. A uniform, conformal SiO
2
coating
24
covers both the outer surface of the raised structures
14
and the underlying substrate
12
. The SiO
2
layer
24
is typically produced by a low pressure chemical vapor deposition (LPCV ) of tetraethyloxysilane (TEOS). The SiO
2
layer
24
conforms itself to the underlying topography. A layer of borophosphosilicate glass (BPSG), or another doped oxide such, as phosphosilicate glass (PSG),
26
covers the SiO
2
layer
24
.
The SiO
2
layer
24
acts as a barrier resistant to the migration of dopants from the BPSG layer
26
into the multilayered structures
14
and substrate
12
. The prior art has unsuccessfully attempted to use “breadloafed” oxide deposits as diffusion barriers between BPSG and underlying conducting regions. These oxides have proven to be inferior for such purposes when they are the only insulator between the BPSG layer
26
and the transistor gate
16
,
18
. The breadloafing deposition technique produces a coating that does not conform to the underlying topography, producing an oxide that is thicker at upper corners of structures such as transistor gates, and which is undesirably thin in lower corners and bottoms of tight areas. Accordingly, the prior art has avoided the use of breadloafed oxides in favor of more desirable conformal oxides.
FIG. 2
shows the structure
10
after a successful vertical etch through the BPSG
26
and the SiO
2
24
layers. The insulating caps
20
and sidewalls
22
act to guide, or self-align, the etch process to form an opening
28
that makes contact with the underlying substrate
12
on a contact area
30
situated adjacent the multilayered structures
14
. This is accomplished by using a chemistry that will etch oxides at a much faster rate than nitrides, such as a low pressure mixture of CHF
3
—Ar—CF
4
with the additive CH
2
F
2
. The subsequent deposition of a conducting material, such as a metal, onto the surface of the semiconductor structure
10
forms a contact that fills the opening
28
. The etching process also invariably erodes away some of the sidewall material
22
, leaving a thinner insulating layer
32
. To avoid a short-circuit between he conducting regions
18
,
16
and the contact, the etch must not break through the sidewalls
22
of FIG.
1
. The original sidewall protection of the silicide conductive layer
18
is thinnest along line
34
in
FIG. 1
, and thus the risk of sidewall breach is highest in that region. After etching, the sidewall insulation
22
is thinnest near the point
36
in FIG.
2
.
FIG. 3
shows an unsuccessful etch of the semiconductor structure
10
in which a sidewall breach
38
exposes the conducting region
18
. The sidewall breach
38
will result in a short-circuit when the conductive material is subsequently deposited in the contact opening
28
. The breach occurred in the region where the original sidewalls were thinnest. This failure can happen due to over-etching, misalignment of the etching mask, or by choosing an etchant that is not suitably selective for oxides. Sidewall breach is a problem for the prior art and is exacerbated by the continual evolution to smaller semiconductor structures. That is, as the structures become smaller, sidewall structures become even thinner and, thus, more prone to sidewall breach.
One method used by the prior art to avoid sidewall breach involves etching vertical openings that are narrower than the space between adjacent sidewalls
32
. The use of narrower openings, however, puts undesirable constraints on photomask alignment. Furthermore, alignment problem are exacerbated as the semiconductor structures are miniaturized. Smaller semiconductor structures have a smaller margin of error in alignment and in timing of the duration of the etching process.
FIG. 4
illustrates an alternative prior art method to avoid sidewall breaches. is This procedure reduces the risk of sidewall breach by employing a two-step etching process. The starting structure is similar to that of FIG.
1
. The first etch proceeds anisotropically under conditions assuring that the BPSG layer
26
is removed more rapidly than the SiO
2
layer
24
. This step terminates before the SiO
2
layer
24
is completely removed. The second step is an isotropic wet etch, which uses an etchant that removes the SiO
2
layer
24
more rapidly than the nitride sidewalls
22
. Accordingly, the second etch exposes the conductive substrate
44
before a sidewall breach occurs. This two-step etch process is undesirable because it is time consuming, costly and unnecessarily complicates the process, increasing the risk that errors will occur. The isotropic etch also runs the risk of laterally etching the BPSG layer
26
making the critical dimension W too wide.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
The invention includes an apparatus having a semiconductor substrate and a contact area on one surface of the substrate. At least one structure is formed on the surface of the substrate adjacent the contact area. An insulative layer extends over at least a portion of the structure. A layer of doped oxide also extends over at least a portion of the structure. An intermediate insulative layer is deposited between the structure and the layer of doped oxide. The intermediate layer has a generally breadloafed form in an area adjacent the structure. The intermediate layer is also resistant to the migration of dopants from the layer of doped oxide into the structure and substrate.
The invention includes a method for making a semiconductor device. The method comprises forming a semiconductor substrate. At least one structure is formed on the surface of the substrate. A first insulative layer is formed over at least a portion of the structure. A second insulative layer, having a generally breadloafed form, is formed over at least a portion of the structure and substrate. The second insulative layer is a also a barrier to the migration of dopants. A layer of doped oxide is formed over the first and second insulative layers.


REFERENCES:
patent: 5286344 (1994-02-01), Blalock et

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