Semiconductor structure implementing sacrificial material...

Details Semiconductor structure implementing sacrificial material... Semiconductor structure implementing sacrificial material...

2005-10-25

2008-09-16

Ghyka, Alexander G (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S631000, C438S637000, C257SE21581, C257SE23144

Reexamination Certificate

active

07425501

ABSTRACT:
A method for making a semiconductor device is provided. The method includes forming transistor structures on a substrate and forming interconnect metallization structures in a plurality of levels through depositing a sacrificial layer. A dual damascene process is performed to etch trenches and vias, and filling and planarizing the trenches and vias. The sacrificial layer is etched throughout the plurality of levels of the interconnect metallization structures, thus leaving a voided interconnect metallization structure. The voided interconnect metallization structure is filled with low K dielectric material, thus defining a low K dielectric interconnect metallization structure.

REFERENCES:
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patent: 6204165 (2001-03-01), Ghoshal
patent: 6333255 (2001-12-01), Sekiguchi
patent: 6642138 (2003-11-01), Pan et al.
patent: 6657302 (2003-12-01), Shao et al.
patent: 6713835 (2004-03-01), Horak et al.
patent: 6717267 (2004-04-01), Kunikiyo

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