Semiconductor storage device and test method therefor

Details Semiconductor storage device and test method therefor Semiconductor storage device and test method therefor

2011-06-28

2011-06-28

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S719000

Reexamination Certificate

active

07971116

ABSTRACT:
Disclosed is a semiconductor device including a BIST provided with a plurality of scan FFs (flip-flops), a data address signal generation circuit unit which respectively generates a data signal and an address signal based on a set value of a scan FF, WEB generation circuit unit which generates a signal WEB which controls writing to and reading data from the semiconductor memory based on an scan FF value, and a test signal control circuit unit which controls the data address signal generation circuit unit and the WEB generation circuit unit, based on a received control signal, controls selectors, and selects and controls, as data and address signals to be supplied to the memory, data signal and address signals from the data address signal generation circuit unit or data and address signals via a user defined circuit.

REFERENCES:
patent: 6779144 (2004-08-01), Hayashi et al.
patent: 2002/0167055 (2002-11-01), Iwasaki
patent: 2004/0107396 (2004-06-01), Barone et al.
patent: 2005/0193293 (2005-09-01), Shikata
patent: 2005-004822 (2005-01-01), None
patent: 2000-0004654 (2000-03-01), None
Korean Patent Office issued a Korean Office Action, Application No. 520020416681, Oct. 27, 2009.

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