Semiconductor storage device and information apparatus using...

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S189090, C365S230060

Reexamination Certificate

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06947342

ABSTRACT:
A semiconductor storage device includes: a memory cell array including a plurality of memory cells which are connected to a plurality of pairs of complementary bit lines; an internal voltage decreasing section for generating a predetermined voltage lower than a power supply voltage; and an equalizing section for performing an equalizing operation to charge the pairs of complementary bit lines to a predetermined equal potential, wherein the internal voltage decreasing section is formed by first and second internal voltage decreasing sections, the equalizing section is formed by a first equalizing section, which is provided at one side of the memory cell array, and a second equalizing section, which is provided at the other side of the memory cell array, the first and second internal voltage decreasing sections supply an electric power to the first and second equalizing sections, respectively.

REFERENCES:
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patent: 5677889 (1997-10-01), Haraguchi et al.
patent: 5689460 (1997-11-01), Ooishi
patent: 5982695 (1999-11-01), Mukai
patent: 6373763 (2002-04-01), Taito et al.
patent: 6515461 (2003-02-01), Akiyama et al.
patent: 0318094 (1989-05-01), None
patent: 59151389 (1984-08-01), None
patent: 4-252497 (1992-09-01), None
patent: 8-69693 (1996-03-01), None
patent: 2001-110184 (2001-04-01), None
Derwent® English Abstract of Japanese Laid-Open Publication No. 4-252497 published on Sep. 8, 1992.
Derwent® English Abstract of Japanese Laid-Open Publication No. 8-069693 published on Mar. 12, 1996.

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