Semiconductor package with pattern leads and method for...

Details Semiconductor package with pattern leads and method for... Semiconductor package with pattern leads and method for...

2006-06-13

2006-06-13

Andujar, Leonardo (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Encapsulated

With specified encapsulant

C438S124000

Reexamination Certificate

active

07061125

ABSTRACT:
A semiconductor package utilizing insulating peripheral sealing portions and pattern leads and methods for manufacturing such semiconductor packages are provided. The semiconductor package includes a substrate on which a semiconductor chip is mounted. The substrate includes a plurality of substrate pads and the semiconductor chip includes a plurality of chip pads on an active surface. The semiconductor chip is surrounded by one or more peripheral sealing layers and conductive lead patterns are formed across the peripheral sealing layer(s) to connect the chip pads to corresponding substrate pads. The chip and lead patterns may be encapsulated and the substrate may also be provided with external connection structures such as solder balls to complete the package.

REFERENCES:
patent: 6437446 (2002-08-01), Uchida
patent: 6747348 (2004-06-01), Jeung et al.
patent: 6750547 (2004-06-01), Jeung et al.
patent: 1019990237329 (1997-02-01), None
patent: 1020000251868 (1997-02-01), None

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