Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2005-03-11
2009-02-03
Zarneke, David A (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S686000
Reexamination Certificate
active
07485955
ABSTRACT:
A variety of non-rectangular IC chips having a stepped or modified periphery or edge profile including one or more recessed or indented peripheral regions are provided for incorporation in modified package configurations, single chip packages and multi-chip assemblies, both stacked and/or planar. In the planar configurations, the recessed regions may be utilized, in cooperation with another appropriately sized IC chip, to increase the packing density of the resulting device. Similarly, in the stacked configuration, the recessed regions may be utilized to provide access to bond pads of lower chips and thereby reduce the need for spacers or peripheral thinning techniques and thereby improve the strength of the resulting assembly and/or reduce the overall height of the stacked structure.
REFERENCES:
patent: 3538400 (1970-11-01), Yanai et al.
patent: 3816906 (1974-06-01), Falckenberg
patent: 5323060 (1994-06-01), Fogal et al.
patent: 5793108 (1998-08-01), Nakanishi et al.
patent: 6359340 (2002-03-01), Lin et al.
patent: 2002/0125556 (2002-09-01), Oh et al.
patent: 2003/0001281 (2003-01-01), Kwon et al.
patent: 2003/0102567 (2003-06-01), Eskildsen
patent: 2003/0178710 (2003-09-01), Kang et al.
patent: 4308705 (1993-09-01), None
patent: 61093613 (1986-05-01), None
patent: 2000-049279 (2000-02-01), None
patent: 2000-058742 (2000-02-01), None
patent: 2000-306865 (2000-11-01), None
patent: 2001-196526 (2001-07-01), None
patent: 1998-067184 (1998-10-01), None
patent: 1998-084225 (1998-12-01), None
patent: 2003-0002476 (2003-01-01), None
Office Action dated Jul. 20, 2007 for corresponding German Patent Application No. 10 2005 016 439.0-33.
Chung Tae-Gyeong
Goh Seok
Kang In-Ku
Kim Jin-Ho
Lee Yong-Jae
Harness Dickey & Pierce PLC
Samsung Electronics Co,. Ltd.
Zarneke David A
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