Semiconductor nanowires having mobility-optimized orientations

Details Semiconductor nanowires having mobility-optimized orientations Semiconductor nanowires having mobility-optimized orientations

2011-05-17

2011-05-17

Nhu, David (Department: 2895)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

C438S311000, C438S775000, C438S513000, C257SE21170, C257SE21320, C257SE21126, C257SE21127, C257SE21229, C257SE21252, C257SE21253, C257SE21267, C257SE21632

Reexamination Certificate

active

07943530

ABSTRACT:
Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed for different crystallographic orientations without excessive thinning or insufficient thinning.

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