Semiconductor memory device with improved bit line precharged ci

Details Semiconductor memory device with improved bit line precharged ci Semiconductor memory device with improved bit line precharged ci

1993-03-30

1994-09-20

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

365190, G11C 700

Patent

active

053495608

ABSTRACT:
A semiconductor memory device includes bit line pair precharge circuits for precharging bit lines in a memory cell array. The semiconductor memory device includes a number of memory cells each sharing a pair of bit lines, each bit line pair together with corresponding memory cells constituting the memory cell array. The memory device further includes a first bit line precharge circuit coupled to a first position along each bit line pair for precharging the respective bit lines under the control of a block selection signal and a write enable signal. A second bit line precharge circuit is connected at a second position along the bit line pair for precharging the respective bit line pair under the control of the write enable signal. A positional distance between the first position and the second position being such as to optimally reduce a bit line precharge time and a write recovery time associated with each bit line pair in the memory cell array.

REFERENCES:
patent: 4656608 (1987-04-01), Aoyama
patent: 4802129 (1989-01-01), Hoekstra et al.
patent: 4888737 (1989-12-01), Sato

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