Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2000-10-12
2002-09-24
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S200000, C365S205000
Reexamination Certificate
active
06456547
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a volatile semiconductor memory device having a function of repairing a stand-by current failure.
2. Description of the Prior Art
There has been a growing trend in manufacturing of semiconductor memory devices with higher integration density. One way to accomplish high integration in a semiconductor memory device is to reduce the size of a memory cell unit to make it possible for integrating more memory cells are integrated within a given area. As integrated memory devices became more dense, the probability of occurrence of defect in memory cells in a memory device increases, thus yield of good semiconductor memory devices decreases. To maintain high yield, redundant memory cells are used. For example, a memory cell having a defect can be replaced with a redundant memory cell under control of a decoding signal generated from a redundancy circuit in a semiconductor memory device.
When a memory cell is tested to be defective, a programmable fuse in a redundancy circuit is cut off to achieve a redundancy operation. If an address signal is input to select a normal memory cell having a defect in a memory access mode, a redundancy decoder, instead of a normal decoder associated with normal memory cells, is enabled by a defective address program using the fuse in the redundancy circuit. As a result, an access is made to a redundancy memory cell instead of the normal memory cell having a defect.
Smaller memory cell units mean smaller spacings or gaps between conductor wires. As such, there is a higher risk of a hard type defect, such as a short-circuit between a bit line and ground or between a pair of bit lines and ground. Such a short-circuit causes a phenomenon called a stand-by current failure, in which excessive current flows through the ground at a stand-by state of a semiconductor memory device. The problem of a stand-by current failure cannot be effectively solved by a redundancy circuit having a fuse to be programmed, by which a normal memory cell having a defect is replaced with a redundancy memory cell. This is because a supply voltage is still applied to a pair of bit lines connected with the normal memory cell having a defect through a pre-charging transistor or the like.
A system for repairing a stand-by current failure by use of a conventional technique was proposed in U.S. Pat. No. 5,390,150 to Choong-Keun Kwak et al., issued on Feb. 14
th
, 1995 being titled “SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANCY STRUCTURE SUPPRESSING POWER CONSUMPTION.” In the aforementioned patent, a cutting element like a fuse is connected to a supply voltage or a pre-charge signal. In case that a stand-by current failure is detected, the fuse is cut off to selectively stop the supply voltage from being supplied to a defective bit line. However, if a repair is made to a unit of a column, a common word line connected with a memory cell associated with a defective bit line may still be used for a cell supply voltage to be applied to the memory cell. Therefore, if there is a short-circuit between a bit line and ground, there is a problem that leaking current flows to the ground through the short-circuited bit line.
Another conventional method and system for repairing a stand-by current failure in a semiconductor memory device can be found in Japanese patent No. Heisei 7-122097. In a 4-transistor cell type static memory device, the power for a leak current compensating circuit is supplied by a bit line pre-set control signal to prevent stand-by leak current from flowing through a defective bit line; otherwise the stand-by leak current would flow in spite of cutting off a fuse connected to the defective bit line.
In the above proposed method, even if a fuse between a voltage supply and a pre-charge transistor is cut off in the case of stand-by current failure, the pre-charge transistor still receives a pre-set control signal at its gate, which alternately shifts between high and low levels in response to transitions between a memory access mode and a stand-by mode of a semiconductor memory device. As a result, a leak current path is formed in the semiconductor memory device. Therefore, it is practically difficult to prevent current from leaking in a stand-by mode or in a memory access mode of a semiconductor memory device.
Therefore, a need exists for a semiconductor memory device having function of repairing a stand-by current failure such that leak current is eliminated in stand-by and memory access modes.
SUMMARY OF THE INVENTION
The present invention is provided to solve the aforementioned problems and other problems in the conventional method and apparatus for repairing stand-by current failure in semiconductor memory devices.
It is an object of the present invention to provide a static random access memory device that can effectively repair a stand-by current failure.
It is another object of the present invention to provide a method for preventing formation of a current path where current flows through a defective bit line.
It is further another object of the present invention to provide a method and apparatus for repairing a hard type defect occurred in a semiconductor memory device, wherein the repair is performed independent of a pre-charge control signal.
It is still another object of the present invention to provide a method and apparatus for preventing leak current from flowing through a defective bit line at a stand-by mode or a memory access mode of a semiconductor memory device.
To accomplish the aforementioned objects of the present invention, there is provided a semiconductor memory device having a plurality of memory cells, and pairs of bit lines, the plurality of memory cells being connected with a pair of bit lines, the semiconductor memory device includes a pre-charging part for pre-charging one pair of the pairs of bit lines in response to a first state control signal output at a stand-by mode of the semiconductor memory device; a bit line charging control part for generating the first state control signal in response to a pre-charge relating signal and generating a second state control signal, the second state control signal being generated when a stand-by current failure occurs due to a defect in the one pair of bit lines, wherein the second state control signal is independent of the pre-charge relating signal and when activated, causes a circuit in the pre-charging part to cut-off supply voltage from being applied to the pair of bit lines; and a bit line floating prevent part for compensatively fixing potential values of the one pair of bit lines having defect so that a cell supply voltage is prevented from being applied to the pair of bit lines during a memory access mode of the semiconductor memory device.
It is preferable that the bit line charging control part comprises a fuse with one of its terminals to be connected to the supply voltage; an NMOS transistor with its drain and gate being commonly connected to the other terminal of the fuse and its source being connected to ground supply voltage; and a NAND gate for receiving a logic state obtained at the other terminal of the fuse and that of a pre-charge relating signal to generate a NAND response as a control signal.
In addition, it is preferable that the bit line floating prevent part comprises a pair of cross-coupled PMOS transistors with drains being commonly connected to the supply voltage and sources being respectively connected to the gates that are also respectively connected to the pair of bit lines in opposite.
In accordance with the other aspect of the present invention, there is provided a method for repairing a stand-by current failure in a static random access memory having memory cells connected with pairs of bit lines in column direction and word lines in row direction, the method comprising the steps of generating a pre-charge prevent signal to prevent a supply voltage from being applied to a pair of bit lines when at least one of the pair of bit lines is def
Kim Du-Eung
Kwak Choong-Keun
Mo Hyun-Sun
F. Chau & Associates LLP
Nelms David
Samsung Electronics Co,. Ltd.
Yoha Connie C.
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