Semiconductor memory device with fast input/output line...

Details Semiconductor memory device with fast input/output line... Semiconductor memory device with fast input/output line...

2000-02-03

2001-03-20

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S190000, C365S238500

Reexamination Certificate

active

06205069

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a circuit for controlling an input/output line (hereinafter, referred to as an “IO line”) precharge in synchronization with a clock signal and a method for IO line precharge.
2. Description of Related Art
Semiconductor memory devices, particularly dynamic random access memories (DRAMs), are widely used in electronic systems for storing digital information. As the electronic systems operate at faster processing speeds, the access time for reading or writing data becomes a significant factor in the DRAM design. Hence, various techniques are used for improving DRAM access time. For example, “nibble mode” operation accesses a series of four sequential bits after accessing the first bit of the series. “Burst mode” operation sequentially accesses a full page or a row of bits after accessing the first bit of the page or the row. In the burst mode operation, after the input of an initial address of the first bit, subsequent addresses for the page or the row are internally generated without input of the subsequent addresses to the DRAM. Thus both the nibble and burst mode operations shorten DRAM access time by eliminating address re-loading delays associated with the subsequent bits.
Thc time from the input of a column address strobe (CASB) command to a data output is often called address access time t
AA
. To decrease the address access time t
AA
, the time required for precharging IO lines to a predetermined voltage, for example, a power supply voltage or half the power supply voltage, must be reduced because a column selection line (CSL) is enabled after IO lines are precharged. This is described below in detail.
FIG. 1
is a block diagram showing a known DRAM device
1
according to the prior art, which operates in synchronization with an externally applied clock signal (an external clock signal). The DRAM
1
has a memory cell array
10
, and the memory cells in the array
10
are arranged at intersections of word lines WLi (i=0 to m) and bit lines BLj (j=0 to n). Each row of the memory array
10
is commonly referred to as a page. The bit lines BLj are divided into two groups, each of which includes pairs of the bit lines BLj. The first group includes bit line pairs BL
0
and BL
1
, BL
4
and BL
5
, . . . , BLn-
3
and BLn-
2
, and the second group includes bit line pairs BL
2
and BL
3
, BL
6
and BL
7
, . . . , BLn-
1
and BLn. A row decoder circuit
20
selects and drives one of the word lines WLi.
IO line pairs IOi and IOiB (i is 2 or more) are at the left side of the array
10
, and IO line pairs IOj and IOjB (j is 2 or more) are at the right side of the array
10
.
FIG. 1
shows only a pair of the IO lines IOi and IOiB and a pair of the IO lines IOj and IOjB. The IO lines IOi and IOiB connect to an IO line driver circuit
30
(a first IO line driver), which in response to a signal CA
8
B drives the IO lines IOi and IOiB with data to be written. A precharge circuit
40
(a first precharge circuit), which is controlled by a precharge signal PIOP_
8
B from a precharge controller
120
, precharges the IO lines IOi and IOiB. Similarly, the IO lines IOj and IOjB connect to an IO line driver circuit
30
′ (a second IO line driver), which drives the IO line pair IOj and IOjB with data to be written in response to a signal CA
8
that is complementary to the signal CA
8
B. A precharge circuit
40
′ (a second precharge circuit), which is controlled by a precharge signal PIOP_
8
from a precharge controller
120
, precharges the IO lines IOj and IOjB.
The bit lines, for example, BL
0
and BL
1
, as a pair, connect either to the IO lines IOi and IOiB or to the IO lines IOj and IOjB through bit line sense amplifiers
50
and column selection transistors ST. The gates of the column selection transistors ST connect to a column decoder circuit
80
through column selection lines CSL
0
to CSLn. In operation, the IO lines IOi and IOiB are precharged, and the IO lines IOj and IOjB have data to be written/read to/from a memory cell associated with a selected word line and a selected bit lines. When the IO lines IOi and IOiB carry data for writing, the IO lines IOj and IOjB are precharged. An access to the array
10
is performed through the IO lines IOi and IOiB or the IO lines IOj and IOjB.
The above-described IO multiplexing and precharging techniques are disclosed in U.S. Pat. No. 4,754,433, entitled “DYNAMIC RAM HAVING MULTIPLEXED TWIN I/O LINE PAIRS”, U.S. Pat. No. 5,761,146, entitled “DATA IN/OUT CHANNEL CONTROL CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE HAVING MULTI-BANK STRUCTURE”, U.S. Pat. No. 5,742,185, entitled “DATA BUS DRIVE CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE”, and U.S. Pat. No. 5,734,619, entitled “SEMICONDUCTOR MEMORY DEVICE HAVING CELL ARRAY DIVIDED INTO A PLURALITY OF CELL BLOCKS”, which are incorporated herein by their entireties.
The precharge controller
120
includes a write interrupt read (WIR) detector
90
, an address transition detector
100
, and a precharge signal generator
110
, and generates the precharge signals PIOP_
8
B and PIOP_
8
when a write interrupt WI occurs. The write interrupt WI starts a write operation through one of the IO lines IOi and IOiB and the IO lines IOj and IOjB and then a write/read operation is performed through the other of the IO lines IOi and IOiB and the IO lines IOj and IOjB. A known circuit diagram of the WIR detector
90
is illustrated in FIG.
2
. Thc WIR detector
90
includes two NOR gates G
1
and G
4
, a transmission gate TG
1
, a latch L
1
including two invertors INV
2
and INV
3
, two NAND gates G
2
and G
3
, an invertor INV
4
, and a pulse generator
91
.
In
FIG. 2
, a signal PWR indicates an operation state at the previous clock cycle, wherein the high and low levels of the signal PWR respectively denote a write operation and a read operation. A signal PWRF indicates an operation state at the present clock cycle. When the signal PWRF is low, a read operation is performed during the present clock cycle. When the signal PWRF is high, a write operation is performed at the present clock cycle. The signal PWRF is not synchronized with the external clock signal. Namely, the signal PWRF is supplied directly into the WIR detector
90
through a buffer circuit (not shown) without setup or hold time. Signals PCF and PCSF, which are not synchronized with external clock signal and are supplied directly into the WIR detector
90
without setup and hold time, indicate a column address strobe signal CASB and a chip select signal CSB, respectively.
The operation of the WIR detector
90
is set forth below with reference to
FIGS. 1 and 2
. A write interrupt read operation occurs when a write operation is performed in association with the IO lines IOi and IOiB, and then a read operation is required in association with the IO lines IOj and IOjB. When the write interrupt read operation occurs, the signal PWRF becomes low. Since the signal PWR is high, an output signal A of the NOR gate G
1
becomes low. When a clock signal PCLKF from a clock buffer
130
is high, an output signal B of the NAND gate G
2
becomes low. This makes an output signal C of the NOR gate G
4
transit from low to high, since both inputs of the NOR gate G
4
are then low. Accordingly, the pulse generator
91
activates a write interrupt read detection signal PWIR to a high level.
On the other hand, when the write operation in association with the IO lines IOi and IOiB is interrupted, and then a write operation is required in association with the second IO lines IOj and IOjB, that is, when a write interrupt write (WIW) operation occurs, the signal PWRF remains high. Since the signal PWR is high, the output signal A of the NOR gate G
1
is low. Successively, when a clock signal PCLKF from the clock buffer
130
is high, the output signal B of the NAND gate G
2
remains high because an input signal of the NAND gate G
2
from the inverter INV
4
is low. Therefore, the input signal C and the output signal PWIR of the p

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