Semiconductor memory device parallel bit test circuits

Details Semiconductor memory device parallel bit test circuits Semiconductor memory device parallel bit test circuits

2011-03-01

2011-03-01

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S733000

Reexamination Certificate

active

07900101

ABSTRACT:
Parallel bit test circuits for use in a semiconductor memory devices are provided which include a first bus that has N bus lines that are configured to transfer a first group of N bits of test result data and a second bus that has N bus lines that are configured to transfer a second group of N bits of test result data. These parallel bit test circuits further include a switching unit that has a plurality of unit switches, where each switch is configured to connect a bus line of the first bus and a respective bus line of the second bus in response to a switching control signal that is applied after the second group of N bits of test result data are output from the second bus, to transfer the first group of N bits of test result data from the first bus to the second bus so as to output a total of 2N bits of test result data through the second bus.

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