Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1991-06-04
1993-11-16
Mottola, Steven
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36518908, G11C 700
Patent
active
052629198
ABSTRACT:
A data input circuit outputs input data in accordance with a write enable signal. A program control circuit generates different data items on the basis of the input data output from the data input circuit and the write enable signal, and turns programming transistors on/off in accordance with the different data items as generated. The programming transistors are connected to a pair of cell transistors forming an EPROM cells, and program into these cell transistors the different data items generated by the write control circuit. A timing circuit delays the timing at which the write enable signal is supplied to the write control circuit, until the input data is established within the data input circuit.
REFERENCES:
patent: 4953129 (1990-08-01), Kobayashi et al.
ISSCC Dig. Tech. Papers, "A 25 ns 16K CMOS PROM Using a 4-Transistor Cell" pp. 162-163 (Feb. 1985).
Atsumi Shigeru
Kuriyama Masao
Miyamoto Junichi
Kabushiki Kaisha Toshiba
Mottola Steven
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