Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2002-06-21
2003-01-07
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Precharge
C365S189110, C365S205000
Reexamination Certificate
active
06504776
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device of a folded bit-line architecture.
2. Description of the Background Art
FIG. 15
is a schematic block diagram showing the configuration of a memory cell array and its peripheral circuits of a conventional semiconductor memory device of a folded bit-line architecture.
A memory cell array
30
includes a plurality of blocks BK
0
to BKn. Each block includes a plurality of pairs of folded bit lines BL and /BL, a plurality of word lines WL, and a plurality of memory cells MC. Each of a plurality of sense amplifiers
100
is connected to two pairs of bit lines BL and /BL.
Referring to
FIG. 15
, in the semiconductor memory device of the folded bit-line architecture, each sense amplifier
100
is connected to two pairs of bit lines BL and /BL. Consequently, the number of sense amplifiers in the semiconductor memory device can be reduced to almost the half of that of a conventional semiconductor memory device.
Reading operation of the semiconductor memory device of
FIG. 15
will be described.
In
FIG. 15
, in the case of selecting block BK
1
, a plurality of pair of bit lines BL and /BL in the region of selected block BK
1
are selected. When attention is paid to a region
301
in
FIG. 15
, sense amplifier
100
in region
301
selects the pair of bit lines BLL and /BLL on the block BK
1
side and disconnects a pair of bit lines BLR and /BLR on the block BK
2
side. Each of the other sense amplifiers
100
selects the pair of bit lines BL and /BL on the block BK
1
side and disconnects the pairs of bit lines BL and /BL on the block BK
2
side and on the block BK
0
side.
After selecting the plurality of pairs of bit lines BL and /BL in block BK
1
by the operation, a not-shown arbitrary word line WL in block BK
1
is selected by a row decoder
40
to thereby select a plurality of memory cells MC (not shown) as targets of the reading operation. The data of selected plural memory cells MC is read out to the corresponding bit line BL or /BL and held by sense amplifier
100
corresponding to the pair of bit lines BL and /BL.
By sequentially changing a column address, the data held by sense amplifier
100
is successively output to not-illustrated data input/output lines IO and IO. A method of successively outputting data of a plurality of memory cells corresponding to a selected word line as described above is called a page mode access.
FIG. 16
is a circuit diagram showing the configuration of region
301
in FIG.
15
.
Referring to
FIG. 16
, sense amplifier
100
is of a flip flop type capable of using an amplified potential as it is for rewriting. Sense amplifier
100
includes P-channel MOS transistors QP
1
to QP
3
and N-channel MOS transistors QN
1
to QN
3
.
To each of bit lines BLL and /BLL, a plurality of memory cells MC are connected. Between bit lines BLL and /BLL, an equalizer
15
is connected. Equalizer
15
includes N-channel MOS transistors QN
4
to QN
6
. Equalizer
15
operates when an activated equalize signal BLEQL is received by gates of transistors QN
4
to QN
6
and precharges the potential of the pair of bit lines BLL and /BLL to VCC/2.
Sense amplifier
100
and the pair of bit lines BLL and /BLL are connected to each other via a selection gate SG
1
. Selection gate SG
1
includes N-channel MOS transistors QN
7
and QN
8
. Transistor QN
7
is connected between bit line /BLL and a sense node SN
1
in sense amplifier
100
. Transistor QN
8
is connected between bit line BLL and a sense node SN
2
in sense amplifier
100
. Transistors QN
7
and QN
8
receive a selection signal SEL by their gates.
To each of bit lines BLR and /BLR, a plurality of memory cells MC are connected. Between bit lines BLR and /BLR, an equalizer
16
is connected. The circuit configuration of equalizer
16
is the same as that of equalizer
15
except that an equalize signal BLEQR is input to the gate of each of transistors in equalizer
16
.
Sense amplifier
100
and the pair of bit lines BLR and /BLR are connected to each other via a selection gate SG
2
. Selection gate SG
2
includes N-channel MOS transistors QN
9
and QN
10
. Transistor QN
9
is connected between bit line /BLR and sense node SN
1
in sense amplifier
100
. Transistor QN
10
is connected between bit line BLR and sense node SN
2
in sense amplifier
100
. Transistors QN
9
and QN
10
receive a selection signal SER by their gates.
The reading operation of the semiconductor memory device having the above-described circuit configuration will be described.
FIG. 17
is a timing chart showing the reading operation in a page mode access of the conventional semiconductor memory device.
Referring to
FIG. 17
, operation performed in the case where the pair of bit lines BLL and /BLL in
FIG. 16
will be described. Before time t
0
, both equalizer activate signals BLEQL and BLEQR are at the H level, so that both of the pair of bit lines BLL and /BLL and the pair of bit lines BLR and /BLR are precharged to VCC/2.
When block BK
1
in
FIG. 15
is selected at time t
0
, out of the two pairs of bit lines connected to sense amplifier
100
in region
301
, the pair of bit lines BLL and /BLL is selected. Therefore, selection signal SEL maintains the H level and selection signal SER is rendered to L level. Consequently, transistors QN
9
and QN
10
in selection gate SG
2
are turned off. As a result, the pair of bit lines BLR and /BLR are not selected.
Subsequently, equalizer activate signal BLEQL input to equalizer
15
is rendered to L level at time t
1
. Consequently, both bit lines /BLL and BLL enter a floating state.
At time t
2
, word line WLn in
FIG. 16
is selected. It is now assumed that, in
FIG. 16
, a memory cell MC
1
connected to word line WLn and bit line /BLL stores L-level data. In this case, the potential on bit line /BLL decreases slightly from VCC/2 at time t
2
.
When sense amplifier activate signal SEN is rendered to H level and sense amplifier activate signal /SEN is rendered to L level at time t
3
, sense amplifier
100
starts operating. Specifically, sense amplifier
100
amplifies the potential on bit line /BLL to a ground potential GND and amplifies the potential on bit line BLL to an internal power supply potential VCC.
Sense amplifier
100
amplifies the potential difference between bit lines /BLL and BLL and then maintains the potentials of bit lines /BLL and BLL.
After each of the plurality of sense amplifiers
100
amplifies the potential difference between the corresponding pair of bit lines BLL and /BLL in block BK
1
, a column address signal output from a column decoder
45
is sequentially changed. A data signal DQi of memory cell MC corresponding to the changed column address is successively output.
As described above, in the page mode access, the sense amplifier amplifies the potential difference between the bit lines of the corresponding pair. After that, until the amplified potential difference is output as data signal DQi, one of the bit lines in the pair is held at internal power supply potential VCC and the other bit line is held at ground potential GND.
At present, a semiconductor memory device is requested to be fabricated finer. By the finer fabrication, interference occurs between an interconnection in a memory cell array of a semiconductor device and a memory cell, and a problem that the charge holding function of the memory cell deteriorates occurs. Particularly, in an SDRAM characterized by a burst output as a kind of the page mode access, a period of holding the potential difference of the bit line pair to be the difference between internal power supply potential VCC and ground potential GND is long in the reading operation. Therefore, when a leak path is included between a bit line and a memory cell due to finer fabrication, deterioration in charge holding capability of the memory cell becomes conspicuous.
FIG. 18
is a schematic diagram for explaining deterioration in charge holding capability of a memory cell in
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