Semiconductor memory device having mesh-type structure of...

Details Semiconductor memory device having mesh-type structure of... Semiconductor memory device having mesh-type structure of...

2002-05-14

2004-03-16

Auduong, Gene (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S201000, C365S222000

Reexamination Certificate

active

06707738

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a structure of a power supply line for supplying a precharge voltage in a dynamic random access memory (DRAM) device.
2. Description of the Related Art
A semiconductor memory device such as a DRAM, as is well known to one skilled in the art, includes memory cell arrays, bit line circuits, and bit line sense amplifiers.
FIG. 1
is a schematic diagram of a conventional semiconductor memory device. Referring to
FIG. 1
, memory cell array
100
includes a plurality of word lines WL
0
~WLm in a row direction, a plurality of bit line pairs BL
0
and /BL
0
in a column direction, and a plurality of memory cells (not shown), which are arranged in a matrix in a region where the plurality of word lines WL
0
~WLm intersect the plurality of bit lines BL
0
and /BL
0
. For convenience, complementary bit lines are expressed {overscore (BL)} in the drawings and /BL in the specification.
Data stored in memory cells are output through the bit line pairs BL
0
and /BL
0
when a high voltage is applied to a corresponding word line, and a bit line sense amplifier
120
senses the variation in voltages loading on the bit line pairs BL
0
and /BL
0
, and thereby the data stored in the memory cells are read. External data are also written into the memory cells through the bit line pairs BL
0
and /BL
0
.
Before the data are read and written from and into the memory cells, the bit line pairs BL
0
and /BL
0
are precharged and equalized into a predetermined precharge voltage VBL. A bit line precharge circuit
211
performs precharging and equalizing of the bit line pairs BL
0
and /BL
0
in response to a precharge signal PEQ.
The precharge voltage VBL is used as a data-discriminating reference voltage. If the level of VBL, or the potential of the precharge voltage VBL is varied at the different locations of the memory array or the semiconductor device, characteristics of the semiconductor memory device may become unstable when data are read and written from and into memory cells.
Thus, the same precharge voltage VBL is supplied to all bit line pairs and is used as a data-discriminating reference voltage in a conventional semiconductor memory device. That is, a common precharge voltage generator (not shown) is used in the conventional semiconductor memory device to generate a precharge voltage VBL which is supplied to all bit line pairs; thus, all bit line pairs receive the same precharge voltage VBL. This conventional structure in supplying VBL may result in lower testing efficiency. For example, during a wafer burn-in test mode, data is input directly into bit line pairs with a precharge voltage line applied, and data is written into memory cells. However, in a structure constituted to supply only a precharge voltage VBL having a single level as with the conventional semiconductor memory device, only one data can be input into all memory cells, and thus the number of test vectors that can be inputted is limited. That is, in a semiconductor memory device having the structure constituted to supply only a precharge voltage VBL, different data cannot be written into adjacent bit line pairs during testing, thereby lowering testing efficiency.
One prior art proposal to overcome the above disadvantage involves a semiconductor memory device having different voltages supplied to adjacent bit line pairs by variably adjusting a time for applying the precharge voltage VBL during a testing operation of a semiconductor memory device.
FIG. 2
is a circuit diagram of a conventional memory cell array of a semiconductor memory device.
Referring to
FIG. 2
, even-numbered bit line pairs BL
0
& /BL
0
~BLn & /BLn among a plurality of bit line pairs BL
0
& /BL
0
~BLn+1 & /BLn+1, which are included in a memory cell array
100
, are precharged and equalized through a first bit line precharge circuit unit
210
at a lower part of the memory cell array
100
, and odd-numbered bit line pairs BL
1
& /BL
1
~BLn+1 & /BLn+1 among the plurality of bit line pairs BL
0
& /BL
0
~BLn+1 & /BLn+1 are precharged and equalized through a second bit line precharge circuit unit
220
at an upper part of the memory cell array
100
. The first and second bit line precharge circuit units
210
and
220
are controlled by first and second precharge signals PEQj and PEQi, respectively.
Thus, the second precharge signal PEQi is discriminated from the first precharge signal PEQj in a test mode, and thereby discriminating voltages are applied to the adjacent bit line pairs. However, in the conventional semiconductor memory device shown in
FIG. 2
, different voltages cannot be simultaneously applied to the adjacent bit line pairs.
Accordingly, a need exists a semiconductor memory device capable of simultaneously applying different voltages to adjacent bit line pairs during a testing operation to increase test efficiency and production yield. Furthermore, a need also exists a semiconductor memory device capable of preventing danger in which data can be unstably discriminated due to a difference in levels of precharge voltages in a normal operation mode in the case of using where two or more precharge voltages.
SUMMARY OF THE INVENTION
A semiconductor memory device is provided, which includes: a plurality of memory cell arrays arranged in a matrix, each of the plurality of memory cell arrays having a plurality of memory cells and a plurality of bit line pairs for outputting and receiving data to and from each of the memory cells; a plurality of bit line precharge circuit units for precharging and equalizing corresponding bit line pairs of the memory cell arrays into predetermined precharge voltages; and a first precharge voltage line and a second precharge voltage line arranged in each region between the plurality of memory cell arrays, wherein during a first mode of operation, the first precharge voltage line and the second precharge voltage line supply a common precharge voltage and during a second mode of operation, precharge voltages having different levels are supplied at the first and the second precharge voltage lines to precharge memory cells adjacent to one another with different precharge voltages.
According to an embodiment of the present invention, the plurality of bit line precharge circuit units include a plurality of upper bit line precharge circuit units positioned at an upper part the plurality of memory cell arrays and a plurality of lower bit line precharge circuit units positioned at a lower part of the plurality of memory cell arrays, the plurality of upper bit line precharge circuit units alternately precharge bit line pairs of a corresponding memory cell array and the plurality of lower bit line precharge circuit units alternately precharge the remaining bit line pairs of the corresponding memory cell array. The first mode is normal operation mode and the second mode is test mode. The precharge voltages having different levels are applied to the bit line pairs from the outside through pads of the semiconductor memory device, and the precharge voltages having the same level are generated in a precharge voltage generator of the semiconductor memory device.
A semiconductor memory device is also provided, which includes: a plurality of memory cell arrays arranged in a matrix, each of the plurality of memory cell arrays having a plurality of memory cells and a plurality of bit line pairs for outputting and receiving data to and from each of the memory cells; a plurality of bit line precharge circuit units for precharging and equalizing corresponding bit line pairs of the memory cell arrays into predetermined precharge voltages; first and second row precharge voltage lines arranged alternately in a first predetermined direction, the first row precharge voltage line for supplying a first precharge voltage to first bit line pairs connected to the first row precharge voltage line and the second row precharge voltage line for supplying a second precharge voltage

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