Semiconductor memory device having local data line pair with...

Details Semiconductor memory device having local data line pair with... Semiconductor memory device having local data line pair with...

2007-07-24

2007-07-24

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S205000, C365S063000

Reexamination Certificate

active

11128878

ABSTRACT:
Disclosed herein is a semiconductor memory device having a pair of local data lines with a delayed precharge voltage application point. The semiconductor memory device of the present invention includes a delay block for delaying the activation time of a block write control signal, thus lengthening the interval starting from the time when data on a pair of bit lines are amplified to the time when a supply voltage is applied to a pair of local data lines. Therefore, according to the semiconductor memory device of the present invention, the time when the supply voltage is applied to the pair of local data lines is the time after data have sufficiently stabilized on the pair of bit lines. Therefore, the semiconductor memory device of the present invention prevents the stabilization speed of the pair of bit lines and the pair of local data lines from decreasing, thus consequently improving the operating speed of the semiconductor memory device.

REFERENCES:
patent: 5978286 (1999-11-01), Chang et al.
patent: 6741511 (2004-05-01), Nakao
patent: 6798704 (2004-09-01), Chen et al.
patent: 01084776 (2001-03-01), None
patent: 100377169 (2003-03-01), None
English Abstract**.

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