Semiconductor memory device for reducing parasitic bit line...

Details Semiconductor memory device for reducing parasitic bit line... Semiconductor memory device for reducing parasitic bit line...

2002-03-19

2003-05-13

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S300000, C257S296000

Reexamination Certificate

active

06563162

ABSTRACT:

This application claims priority from Korean Patent Application No. 2001-14588, filed on Mar. 21, 2001, the contents of which are incorporated herein by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of fabricating the same and, more particularly, to a semiconductor memory device for reducing parasitic bit line capacitance and a method of fabricating the same.
2. Description of the Related Art
It is important to improve the sensitivity of a sense amplifier for more accurately sensing and amplifying data stored in memory cells of semiconductor memory devices, e.g., DRAM devices. Thus, the electric potential difference &Dgr;V=(Vcc/2)/[1+(Cb/Cs)] input to both ends of the sense amplifier must be increased. Here, Vcc, Cb, and Cs represent supply voltage, bit line capacitance, and storage capacitance, respectively.
In order to increase the electric potential difference (&Dgr;V), the ratio of Cb/Cs must be decreased. However, as the integration density of DRAM devices increases, the length of a bit line is increased. Consequently, the bit line capacitance is increased, but the electric potential difference is decreased. Also, as the integration density of DRAM devices increases, supply voltage decreases with scaling down of transistors. This further decreases the electric potential difference. To improve the sensitivity of the sense amplifier, one common approach is to increase storage capacitance. However, as the integration density of DRAM devices increases, the area of a storage capacitor is inevitably reduced and, thus, it becomes more difficult to increase storage capacitance. Consequently, bit line capacitance needs to be decreased from its present levels.
Parasitic bit line capacitance can be classified into four types: capacitance between a bit line and a p-well, capacitance between a bit line and a word line, capacitance between a bit line and a bit line, capacitance between a bit line and a storage electrode. However, parasitic bit line capacitance is mostly generated between the bit line and the storage electrode. In particular, if a buried contact, made of polysilicon to which a storage electrode and a pad are connected, is formed using a self-aligned contact technique, there is a large parasitic bit line capacitance between the storage electrode and the bit line.
Accordingly, there is an immediate need to reduce parasitic bit line capacitance to improve the sensitivity of a sense amplifier.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a semiconductor memory device for reducing parasitic bit line capacitance.
It is another object of the present invention to provide a method of fabricating the semiconductor memory device for reducing parasitic bit line capacitance.
Accordingly, to achieve the above first object, according to an embodiment of the present invention, there is provided a semiconductor memory device. The semiconductor device includes a conductive pad formed on a semiconductor substrate and a first interlayer insulating layer having a first contact hole that exposes the conductive pad. The first interlayer insulating layer is formed on the conductive pad and the semiconductor substrate. Bit line stacks are formed on the first interlayer insulating layer. The bit line stack serves as a bit line. Preferably, the bit line stack is a stack layer including a bit line conductive layer and a bit line capping layer.
Bit line spacers, which are formed from a combination of materials having different dielectric constants, are formed on the sidewalls of the bit line stack to reduce parasitic bit line capacitance. Preferably, the bit line spacers are stack layers of nitride, oxide, and silicon nitride on both sidewalls of the bit line stack. The bit line spacer are stack layers including oxide and nitride on both side walls of the bit line satack. A second interlayer insulating layer having a second contact hole that exposes the bit line stack is formed on the bit line stack. A conductive plug fills the first and second contact holes. A storage electrode of a capacitor is connected to the conductive pad via the conductive plug.
According to another embodiment of the present invention, there is a semiconductor memory device. Gate stacks are formed on a semiconductor substrate. Gate spacers are formed on the sidewalls of the gate stacks. Preferably, the gate stacks are a stack layer including a gate dielectric layer, a gate conductive layer, and a gate capping layer. A first interlayer insulating layer having a first contact hole that exposes the semiconductor substrate between the gate spacers is formed. Bit line contact (DC) and storage node contact (BC) pads fill the first contact hole. A second interlayer insulating layer having a DC contact hole which exposes the DC pad is formed. A bit line stack, which fills the DC contact hole, is connected to the DC pad. Preferably, the bit line stack is a stack layer including a barrier metal layer, a bit line conductive layer, and a bit line capping layer.
Bit line spacers, which are formed from a combination of materials having different dielectric constants to reduce parasitic bit line capacitance, are formed on both sidewalls of the bit line stack. Preferably, the bit line spacers are stack layers of nitride, oxide, and silicon nitride on the sidewalls of the bit line stack. The bit line spacers are stack layers including oxide and nitride on both sidewalls of the bit line stack. A third interlayer insulating layer having a second contact hole that exposes the BC pad is self-aligned with the bit line spacers. A conductive plug fills the second contact hole. A storage electrode which is connected to the BC pad via the conductive plug.
To achieve the second object, according to an embodiment of the present invention, there is provided a method of fabricating a semiconductor memory device. A conductive pad is formed on a semiconductor substrate. A first interlayer insulating layer is formed to cover the conductive pad. A bit line stack is formed to expose the interlayer insulating layer. Preferably, the bit line stack is a stack layer including a bit line conductive layer and a bit line capping layer.
A combination layer of materials having different dielectric constants is formed on the semiconductor substrate, on which the bit line stack is formed, to reduce parasitic bit line capacitance. The combination layer is anisotropically-etched to form bit line spacers on the sidewalls of the bit line stack. Preferably, the bit line spacers are stack layers of nitride, oxide, and nitride on both sidewalls of the bit line stack. The bit line spacers are stack layers including oxide and nitride on both sidewalls of the bit line stack. A second interlayer insulating layer is formed to fill spaces between the bit line spacers. The first and second interlayer insulating layers are patterned to form a contact hole, which is self-aligned with the bit line spacers, to expose the conductive pad. A conductive plug is formed to fill the contact hole. A storage electrode of a capacitor is formed on the conductive plug.
According to another embodiment of the present invention, a method of fabricating a semiconductor memory device is provided. Gate stacks are formed on a semiconductor substrate. Gate spacers are formed on the sidewalls of the gate stack. Preferably, the gate stack is a stack layer including a gate dielectric layer, a gate conductive layer, and a gate capping layer. A first interlayer insulating layer having a first contact hole is formed to expose the semiconductor substrate between the gate spacers. DC and BC pads are formed to fill the first contact hole. Preferably, a conductive layer is formed and planarized on the semiconductor substrate, on which the first contact hole is formed, to form the DC and BC pads. A second interlayer insulating layer having a DC contact hole is formed to expose the DC pad. A bit line stack is formed to fill t

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