Semiconductor memory device comprising circuit for...

Details Semiconductor memory device comprising circuit for... Semiconductor memory device comprising circuit for...

2002-12-20

2004-11-02

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S205000, C365S230060

Reexamination Certificate

active

06813204

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having reduced electric current consumption wherein a data line pair share an electric charge during a data write operation.
2. Description of the Related Art
Generally, a semiconductor memory device needs a circuit for precharging a data line to a predetermined voltage level before performing an operation for writing external data.
FIG. 1
is a diagram of a semiconductor memory device
100
having a prior art precharge circuit, and
FIG. 2
is a table showing voltage levels of data line pairs according to the operation of the semiconductor memory device
100
. The voltage level corresponding to a “high” logic level, shown in
FIG. 2
, is the difference (Vcc−Vt) of a voltage supply (Vcc) and a transistor threshold voltage (Vt).
The semiconductor memory device
100
comprises a data input driver
110
, a first data line pair charge circuit
120
, a switching circuit
130
, and a second data line pair charge circuit
140
. Data outputs from the second data line pair (DATA
2
,/DATA
2
) are input to a memory array (not shown).
The data input driver
110
is connected to the first data line pair (DATA
1
, /DATA
1
). The data input driver
110
drives the first data line pair (DATA
1
, /DATA
1
) after receiving predetermined data from a data input terminal (DATA_IN).
The first data line pair charge circuit
120
, in response to a control signal (DP
1
), precharges the first data line pair (DATA
1
, /DATA
1
) to a predetermined voltage level. The second data line pair charge circuit
140
, in response to a control signal (DP
2
), precharges the second data line pair (DATA
2
, /DATA
2
) to a predetermined voltage level.
The switching circuit
130
, in response to a selection signal (SEL), connects the first data line pair (DATA
1
,/DATA
1
) with the second data line pair (DATA
2
, /DATA
2
).
While precharging a data line, predetermined control signals (DP
1
, DP
2
) are transited to a “low” logic level (ground (VSS) level), and both the first data line pair (DATA
1
, /DATA
1
) and the second data line pair (DATA
2
, /DATA
2
) are precharged to a “high” logic level in response to predetermined control signal (DP
1
, DP
2
). The “high” logic level is the level of the voltage supply (Vcc) or voltage supply−threshold voltage (Vcc−Vt).
When a data write operation is performed, DATA
1
is in a “high” logic level while /DATA
1
is transited to a “low” logic level, or DATA
1
is transited to a “low” logic level while /DATA is in a “high” logic level in the first data line pair (DATA
1
, /DATA
1
) according to data driven by the data input driver
110
. By the operation of the switching circuit
130
, the second data line pair (DATA
2
, /DATA
2
) are transited to substantially the same voltage levels as the first data line pair (DATA
1
, /DATA
1
).
After finishing the data write operation, the semiconductor memory device
100
returns to the precharge state. In this case, both the first data line pair (DATA
1
, /DATA
1
) and the second data line pair (DATA
2
, /DATA
2
) are precharged to the voltage supply (Vcc), as described above.
At this time, one line of the first data line pair (DATA
1
, /DATA
1
) and one line of the second data line pair (DATA
2
, /DATA
2
) can be transited to a “low” logic state by a write operation from a “high” logic state by the precharge operation, and can be transited to a “high” logic level again by a precharge operation. Therefore, these lines consume electric current as write operations and precharge operations are repeated.
Therefore, a need exists for a semiconductor memory device having reduced electric current consumption wherein a data line pair share an electric charge during a data write operation.
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, a semiconductor memory device exhibits reduced electric current consumption over repeated write/precharge operations.
According to an embodiment of the present invention, a semiconductor memory device comprises a precharge circuit that precharges a first data line pair and a second line pair to respective predetermined voltage levels in a precharge operation state. The semiconductor memory device comprises a data input driver, which receives data and drives the data to the first data line pair, and a control circuit, which in response to a selection signal, connects or disconnects the first data line pair with the second data line pair, and in response to the selection signal, connects or disconnects one line of the first data line pair to one of the second data line pair.
It is preferable that the precharge circuit comprises a first precharge circuit, which in response to a first control signal, precharges the first data line pair to a first voltage level, and a second precharge circuit, which in response to a second control signal, precharges the second data line pair to a second voltage level.
It is preferable that the first voltage level is different from the second voltage level.
It is preferable that the control circuit controls, in response to the selection signal, the voltage level of one line of the first data line pair and the voltage level of one line of the second data line pair change to a predetermined voltage level between the first voltage level and the second voltage level.
The control circuit comprises a first NOR gate for receiving a first line of the second data line pair and the selection signal and outputting a first logic signal, and a second NOR gate for receiving a second line of the second data line pair and the selection signal and outputting a second logic signal. The control circuit further comprises an NMOS transistor comprising a gate for receiving the first logic signal, a source coupled to the first line of the second data line pair and a drain coupled to a second line of the first data line pair, and an NMOS transistor comprising a gate for receiving the second logic signal, a source coupled to the second line of the second data line pair and a drain coupled to a first line of the first data line pair.
According to another embodiment of the present invention, a semiconductor memory device comprises a first precharge circuit, which precharges a first data line pair to a first voltage level in a precharge operation state, and a second precharge circuit, which precharges a second data line pair to a second voltage level in a precharge operation state. The semiconductor memory device further comprises a data input driver, which receives data and drives the data to the first data line pair, a switch, which in response to a selection signal, connects or disconnects the first data line pair with the second data line pair, and a charge-sharing control circuit, which in response to the selection signal, makes one line of the first data line pair and one line of the second data line pair share charge.
It is preferable that the first voltage level is different from the second voltage level.
It is preferable that the charge-sharing control circuit controls, in response to the selection signal, the voltage level of one line of the first data line pair and the voltage level of one line of the second data line pair change to a predetermined voltage level between the first voltage level and the second voltage level.
According to another embodiment of the present invention, a semiconductor memory device comprises a first data line pair, a second data line pair, and a data input driver, which is connected to the first data line pair and drives input data to the first data line pair. The semiconductor memory device further comprises a charge-sharing control circuit, which is connected between the first data line pair and the second data line pair, and in a first step of a precharge operation, connects one line of the first data line pair and one line of the second data line pair.
It is preferable that the first data line pair is precharged to a first voltage level in a second step

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