Semiconductor memory device, chain memory device, and data proce

Details Semiconductor memory device, chain memory device, and data proce Semiconductor memory device, chain memory device, and data proce

1994-06-14

1996-12-10

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518901, G11C 700

Patent

active

055838146

ABSTRACT:
An arrangement is provided for the input level of an output buffer from fluctuating when a memory device goes from an active state to an inactive state. To achieve this, a level holding circuit is provided at a point connecting an output of a sense circuit for amplifying a signal read from a memory array to an input of an output buffer. The level holding circuit is constituted so that, when the sense circuit goes from an active state to an inactive state, the level holding circuit holds an input level of the output buffer at a time immediately before the sense circuit goes inactive.

REFERENCES:
patent: 4701889 (1987-10-01), Ando
patent: 4894803 (1990-01-01), Aizaki
patent: 5239506 (1993-08-01), Dachtera et al.
patent: 5307319 (1994-04-01), Kohketsu et al.
patent: 5311471 (1994-05-01), Matsumoto et al.

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