Semiconductor memory device capable of improving data...

Details Semiconductor memory device capable of improving data... Semiconductor memory device capable of improving data...

2000-04-05

2002-01-08

Lebentritt, Michael (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S042000, C365S221000, C365S230080, C365S233100

Reexamination Certificate

active

06337809

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 99-11826, filed on Apr. 6, 1999, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a double data rate synchronous DRAM (DDR SDRAM) and a method for controlling read and write operations of a DDR SRAM.
In a single data rate synchronous DRAM (SDR SDRAM), the input and output of data through a data input and output pin DQ is performed at the rising edge of a clock. In the DDR SDRAM, the input and output of data through The data input and output pin DQ is performed at the rising and falling edges of the clock.
In general, the amount of data processed in one clock cycle is called a prefetch unit. The prefetch unit of the SDR SDRAM is 1. The prefetch unit of the DDR SDRAM is 2.
FIG. 1
is a timing diagram for comparing the data processing speed and the efficiency of the data input and output pin DQ in the SDR SDRAM with the data processing speed and the efficiency of the data input and output pin DQ in the DDR SDRAM. Here, a case where the CAS latency (CL) is 2.5 and the burst length (BL) is 4 is shown.
In an arithmetical sense, since a DDR SDRAM processes twice the data of a SDR SDRAM in one clock cycle, the processing speed of the DDR SDRAM should be double that of the SDR SDRAM. However, the processing speed of the DDR SDRAM is not double the processing speed of the SDR SDRAM. Namely, as shown in
FIG. 1
, in the DDR SDRAM, the read command (RD) should be received after write data D
0
through D
3
are completely written.
In other words, the read command RD should be received after the lapse of a write recovery time (t
WR
), and read data Q
0
through Q
3
are output after the lapse of clock cycles corresponding to the CAS latency after the read command RD is received. Thus, the processing speed of the DDR SDRAM is not double the processing speed of the SDR SDRAM. Accordingly, the efficiency of the data input and output pin DQ in the DDR SDRAM is lower than the efficiency of the data input and output pin DQ in the SDR SDRAM. Referring to
FIG. 1
, the efficiency of the data input and output pin DQ in the SDR SDRAM is 67% and the efficiency of the data input and output pin DQ in the DDR SDRAM is 44%.
SUMMARY OF THE INVENTION
To solve the above problem, it is an object of the present invention to provide a DDR SDRAM capable of improving the data processing speed and the efficiency of The data input and output pin DQ.
It is another object of the present invention to provide a method for controlling the read and write of the DDR SDRAM that is capable of improving the data processing speed and the efficiency of the data input and output pin DQ.
Accordingly, to achieve the first object, the DDR SDRAM according to the present invention comprises a memory cell array storing memory data, a data storage circuit to temporarily store write data when a read command is received during a write operation and to output the stored write data to the memory cell array after a read operation is completed, an address storage circuit to temporarily store write addresses corresponding to the write data when the read command is received during the write operation and to output the stored write addresses to the memory cell array after the read operation is completed, and a control signal generator for generating a plurality of control signals for controlling the data storage circuit and the address storage circuit in response to a write command and the read command, wherein the write data stored in the data storage circuit is output when read addresses received during the read operation coincide with the write addresses stored in the address storage circuit.
Preferably, the data storage circuit and the address storage circuits are both first-in first-out buffers. In addition, the number of write data items stored in the data storage circuit preferably varies according to the CAS latency of the semiconductor memory device. Similarly, the number of addresses stored in the address storage circuit preferably varies according to the CAS latency of the semiconductor memory device.
The DDR SDRAM may also comprise a data input and output pin for providing the write data to the data storage circuit. In addition, the DDR SDRAM may also comprise a selector circuit connected to the memory array and the data storage circuit, for receiving the write data stored in the data storage circuit and outputting the received write data through the data input and output pin when the read addresses received during the read operation coincide with the write addresses stored in the address storage circuit, and for receiving the memory write data stored in the memory array and outputting the received memory data through the data input and output pin when the read addresses received during the read operation does not coincide with the write addresses stored in the address storage circuit.
To achieve the second object, the method for controlling the read and write of the DDR SDRAM according to the present invention comprises temporarily storing write data when a read command is received during a write operation and outputting the stored write data to the memory cell array after a read operation is completed, temporarily storing addresses corresponding to the write data when the read command is received during the write operation and outputting the stored addresses to the memory cell array after the read operation is completed, and comparing read addresses during the read operation with the stored addresses and outputting the stored write data rather than the data of the memory cell array when the read addresses during the read operation coincide with the stored addresses.
Preferably, the number of stored write data items and the number of stored addresses varies according to the CAS latency of the semiconductor memory device.


REFERENCES:
patent: 5404480 (1995-04-01), Suzuki
patent: 5717653 (1998-02-01), Suzuki
patent: 5838631 (1998-11-01), Mick
patent: 6134180 (2000-10-01), Kim et al.
patent: WO 95/02248 (1995-01-01), None
patent: WO 96/30838 (1996-10-01), None

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