Semiconductor memory device and test pattern data generating...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S720000

Reexamination Certificate

active

10954870

ABSTRACT:
A semiconductor memory device includes a mode setting register for generating a parallel bit test signal and a code according to an externally applied mode setting register code in response to a mode setting command; a data input circuit for receiving and outputting at least one bit of externally applied data in response to a write command; and a test pattern data generating circuit for receiving the parallel bit test signal and a predetermined bit from the code to generate a test pattern data in response to the at least one bit of externally applied data received from the data input circuit.

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patent: 6445627 (2002-09-01), Nakahara et al.
patent: 6636998 (2003-10-01), Lee et al.
patent: 6909650 (2005-06-01), Ryu et al.

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