Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-08-14
2007-08-14
Britt, Cynthia (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S720000
Reexamination Certificate
active
10954870
ABSTRACT:
A semiconductor memory device includes a mode setting register for generating a parallel bit test signal and a code according to an externally applied mode setting register code in response to a mode setting command; a data input circuit for receiving and outputting at least one bit of externally applied data in response to a write command; and a test pattern data generating circuit for receiving the parallel bit test signal and a predetermined bit from the code to generate a test pattern data in response to the at least one bit of externally applied data received from the data input circuit.
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Chae Moo-Sung
Choi Hye-In
Britt Cynthia
Marger & Johnson & McCollom, P.C.
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