Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
1999-11-10
2001-02-27
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S233100
Reexamination Certificate
active
06195296
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and system, and more particularly to a semiconductor memory device which can make a progress in transmission of an internal control signal which might be delayed due to the load on a data line and which can prevent data conflict on a data bus when data is transmitted to the data bus located between semiconductor memory devices and a processor.
2. Description of the Related Art
A conventional semiconductor memory device generates an internal output control signal by inputting an output control signal from outside, transmits it to data output drivers connected to respective data input/output pins to enable or disable outputting of data. Therefore, the single internal output control signal is used as a control signal for a plurality of data output drivers.
In this case, the time for transmitting the internal output control signal is delayed because of the load on the data transmission line because the internal output control signal is transmitted to a plurality of data output drivers.
Accordingly, in case that the semiconductor memory device is operating at a low speed, a margin is sufficiently secured between the input/output data so that it can be negligible that the transmission of the internal output control signal is delayed. On the other hand, in case that the semiconductor memory device is operating at a high speed, a margin is not so sufficiently provided between the input/output data that it becomes impossible for the device to successfully drive at a high speed.
Furthermore, the system having the conventional semiconductor memory device is constructed with two semiconductor memory devices sharing a data bus and a processor. In the system, data is transmitted via the data bus when the two semiconductor memory devices are enabled or disabled by the processor.
When the system constructed with semiconductor memory devices sharing the data bus is operating at a low speed, the margin is provided between the input/output data transmitting on the data bus so sufficiently that data conflict may be available. However, when the system is operating at a high speed, the margin is not sufficiently secured between the input/output data transmitting on the data bus so that data conflict may happen.
In other words, in the operations to output data from the two semiconductor memory devices commonly connected to a data bus, after the data output driver completes transmitting data to the data output pin of the one semiconductor memory device and is disabled, but before the data inputted at the data bus is completely transmitted to the processor, if the data output driver is enabled to transmit data to the data output pin of the other semiconductor memory device and transmit the data to the commonly shared data bus, data conflict may happen on the data bus.
In order to solve the aforementioned problems, a technique titled “clocked logic circuitry preventing double driving on shared data bus” has been disclosed to add a dummy cycle at every time that the drivers driving the data bus are changed. In other words. That is, after the driver operated at the previous cycle is disabled, a dummy cycle is added to complete disabling the driver and to enable another driver operating at the current cycle. However, there is a disadvantage in the aforementioned method in that the additional dummy cycle lowers the efficiency of the data bus to make it impossible to apply at a system operating at a high speed.
Also, another technique titled “driver for tri-state bus” has been disclosed at U.S. Pat. No. 5,646,553 to solve the aforementioned problem. Data is transmitted to the data bus during the first half cycle of a clock signal, and the data is then kept there during the second half cycle thereof. However, there is also a problem in this method in that an additional consideration should be made in the course of designing the system to provide all the data buses with keepers which include latches to keep the transmitted data on the data buses.
The present invention is disclosed to solve the aforementioned problem as the data conflict on the shared data bus in the prior art is caused because there is only one internal output control signal for controlling the data output drivers of the semiconductor memory devices and because the single control signal simultaneously controls all the data output drivers connected to the data input/output pins, which increases the load on the data line so greatly as to slow down the speed of transmitting the control signal.
The aforementioned problems can also be solved by mismatching the size of transistors located on the path which generates the internal output control signal to thereby speed up the time for enabling or disabling the internal output control signal. However, if the time for enabling the internal output control signal is shortened, data conflict may happen on the system with the shared data bus. On the other hand, if the time for disabling the internal output control signal is shortened, it may be impossible to make the system operate at a high speed because the time for accessing data lags in spite of one advantage of preventing the data conflict on the shared data bus.
On the other hand, the time for enabling and disabling the internal output control signal can be shortened by using an identically big transistors on the path to generate the internal output control signal. However, in this case the size of all the transistors which generate the internal output control signal increases to proportionally influence on the switching current, and the increased current load slows down the speed of transmitting the signal more adversely than when the size of transistors is mismatched.
SUMMARY OF THE INVENTION
The present invention is disclosed to solve the aforementioned problems and it is an object of the present invention to provide a semiconductor memory device which can improve the speed to transmit an internal output control signal for controlling data output drivers.
It is another object of the present invention to provide a system having semiconductor memory devices which can prevent data conflict on a commonly shared data bus located between the semiconductor memory devices and a processor.
In order to accomplish the first object, the semiconductor memory device of the present invention comprises:
at least two groups of data input/output drivers;
a control circuit to generate first and second control signals in response to an externally-supplied clock signal, read/write control signal, and chip selection control signal, the control circuit asserting the first control signal when the externally-supplied signals indicate a read command for a current memory cycle and the externally-supplied signals indicated a write command or a non-selection command for the preceding memory cycle, the control circuit asserting the second control signal when the signals indicate a write command or a non-selection command for a current memory cycle and the control signals indicated a read command for the preceding memory cycle; and
a repeater for each group of data input/output drivers, each repeater generating an internal output control signal for its driver group, the assertion of the internal output control signal responsive to the first control signal, and the deassertion of the internal output control signal responsive to the second control signal.
To achieve the second object of the present invention, a system comprises first and second semiconductor memory devices sharing a data input/output bus, and a processor that transmits a clock signal, a read/write control signal and a chip selection control signal to control operations of the first and second semiconductor memory devices, wherein each of the semiconductor memory devices comprises:
at least two groups of data input/output drivers;
a control circuit to generate first and second control signals in response to an externally-supplied clock signal, read/write control signal, and chip selection control s
Le Vu A.
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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