Semiconductor memory device and signal processing system

Details Semiconductor memory device and signal processing system Semiconductor memory device and signal processing system

2007-10-16

2007-10-16

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S185080, C365S230080

Reexamination Certificate

active

11126302

ABSTRACT:
A semiconductor memory device able to read out data at a high speed continuously, provided with, corresponding to a plurality of banks, current address registers for holding addresses for reading data of cell arrays, reserved address registers able to receive in advance and hold reserved addresses for next read operations from the outside, and bank control circuits for making the current address registers hold reserved addresses held in the reserved address registers, making the data be read out, and making the data latch circuits hold the data when the data read out from the cell arrays of the banks by addresses held in the current address registers and held in the data latch circuits become able to be transferred to the outside, and a signal processing system relating to the same.

REFERENCES:
patent: 4685088 (1987-08-01), Iannucci
patent: 4888741 (1989-12-01), Malinowski
patent: 5592435 (1997-01-01), Mills et al.
patent: 5594704 (1997-01-01), Konishi
patent: 5796675 (1998-08-01), Jang
patent: 5970020 (1999-10-01), Ong
patent: 7091971 (2006-08-01), Morein
EPO Search Report, Oct. 19, 2005.

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