Semiconductor memory device and method of testing the device

Details Semiconductor memory device and method of testing the device Semiconductor memory device and method of testing the device

2006-01-10

2006-01-10

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S189070, C365S189120, C365S200000, C365S225700

Reexamination Certificate

active

06985395

ABSTRACT:
A semiconductor memory device is disclosed, which includes a memory cell array including memory cells arranged in rows and columns, a word line, a bit line, a row decoder and a column decoder, a sense amplifier provided for each of the columns of the memory cell array, a write latch circuit configured to store externally input data and sets data of one row of the memory cell array in the sense amplifiers in test mode, a read latch circuit configured to store data of one row, which is read from the memory cell array and set in the sense amplifiers in test mode, a first comparison circuit configured to compare the data stored in the write latch circuit and the data stored in the read latch circuit, and a first comparison result register configured to store a comparison result of the first comparison circuit.

REFERENCES:
patent: 6032274 (2000-02-01), Manning
patent: 6141286 (2000-10-01), Vo et al.
patent: 2001-256798 (2001-09-01), None
Toshiba Digital Integrated Circuit Technical Data (TC528257J/SZ/FT-70, TC528257J/SZ/FT-80, dated May 18, 1994.
Toshiba CMOS Memory Data Book, Toshiba Corporation, 1996, p. 92.

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