Semiconductor memory device and method for manufacturing the...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S618000, C438S622000, C438S629000, C438S640000, C438S652000, C438S666000, C438S778000

Reexamination Certificate

active

07462523

ABSTRACT:
A conductive portion connects a lower conductive layer formed on a semiconductor substrate provided in a first interlayer insulating layer to an upper conductive layer formed on the lower conductive layer, and provided in a second interlayer insulating layer. This portion is divided into at least one plug and a pad. At least one plug is formed in a first interlayer insulating layer and the lower part of a second interlayer insulating layer. The second interlayer insulating layer is divided into a plurality of interlayer insulating layers so that upper and lower widths of the divided plugs formed in the divided portion of the second interlayer insulating layer are not greatly different from each other. The pad formed on the upper portion of the second interlayer insulating layer has an upper width such that the upper conductive layer connected to the pad is not undesirably connected to an adjacent upper conductive layer via the pad.

REFERENCES:
patent: 5519237 (1996-05-01), Itoh et al.
patent: 5693971 (1997-12-01), Gonzalez
patent: 6291335 (2001-09-01), Schnabel et al.
patent: 6365453 (2002-04-01), Deboer et al.
patent: 6407464 (2002-06-01), Terauchi
patent: 6451651 (2002-09-01), Park et al.
patent: 2001/0005624 (2001-06-01), Aoyagi et al.
patent: 2001/0034106 (2001-10-01), Moise et al.
Stanley Wolf“Silicon Processing For The VLSI ERA” vol. 3 the submicron Mosfet, 1995 pp. 4.

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