Semiconductor memory device and manufacturing method thereof

Details Semiconductor memory device and manufacturing method thereof Semiconductor memory device and manufacturing method thereof

1998-06-15

2000-07-11

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438238, 438253, 438381, 438396, H01L 218234

Patent

active

060872136

ABSTRACT:
A method of making a semiconductor memory device is discussed, which has a long refresh time and offers high reliability by minimizing junction leakage current, resulting in increased charge retention time. This is achieved by optimizing the diffusion layer junction depth formed in a deeper region of the semiconductor substrate which is in electrical contact with the impurity diffusion layer. Typically, junction depth is in excess of 0.1 .mu.m. Two methods for achieving such a structure are also provided. In one method, implantation voltage in excess of 80 KeV is used to implant P ions to form a high carrier concentration profile at a junction depth of greater than 0.1 .mu.m. In another method, implantation process are carried out in two steps so as to force the previously implanted ions deeper into the storage node electrode, and a subsequent heat treatment is carried out to further distribute the dopant ions into the substrate of the semiconductor substrate so as to disperse crystal defects into the substrate. The resulting structure is essentially free of crystal defects which cause current leakage from the boundary region between the dopant diffusion layer and the substrate in the conventional memory cell structure.

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Wolf et al. Silicon Processing for the VLSI Era, vol. I, Lattice Press, 1986, pp. 325-327.

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