Semiconductor memory device and layout method thereof

Details Semiconductor memory device and layout method thereof Semiconductor memory device and layout method thereof

2008-09-02

2010-10-05

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S063000, C365S189110, C365S205000

Reexamination Certificate

active

07808852

ABSTRACT:
Example embodiments relate to a semiconductor memory device, for example, a semiconductor memory device including an efficient layout circuit and method thereof. The method may include sharing a first active area between a first precharger and a second precharger and sharing a second active area between a third precharger and a fourth precharger. The semiconductor memory device may include a level shifter configured to receive a first precharge control signal and boost a logic high level of the first precharge control signal to an external power supply voltage level to output a boosted first precharge control signal. The semiconductor memory device may further include first, second, third and fourth prechargers. The first and third prechargers may be configured to precharge data signals transmitted to a first and second pair of local input/output data lines to the first precharge voltage in response to the boosted first precharge control signal during a data read operation.

REFERENCES:
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patent: 2005-340367 (2005-12-01), None
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Abstract of Korean Patent Publication No. 1020040014742 published Feb. 18, 2004.
Abstract of Korean Patent Publication No. 1020030069653 published Aug. 27, 2003.

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