Semiconductor memory device and fabricating method thereof

Details Semiconductor memory device and fabricating method thereof Semiconductor memory device and fabricating method thereof

2001-03-16

2002-10-08

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S241000, C438S396000, C257S298000, C257S308000, C257S311000

Reexamination Certificate

active

06461911

ABSTRACT:

BACKGROUND OF THE INVENTION
The present application claims priority under 35 U.S.C. §119 to Korean Application No. 2000-28658 filed on May 26, 2000, which is hereby incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention relates to a semiconductor memory device and a fabricating method thereof, and more particularly, to a dynamic random access memory (DRAM) device and a fabricating method thereof.
2. Description of the Related Art
When manufacturing highly integrated DRAM devices, problems can occur in each step of a process for manufacturing the semiconductor memory devices. In order to alleviate such problems, materials of semiconductor memory devices can be changed and new design techniques can be adopted in the integration schemes thereof. There are many types of integration schemes in which new design techniques are adopted. Most recently, representative integration schemes in a process for manufacturing DRAM devices for which a design rule of below 0.17 &mgr;m is used, include an isolation layer manufactured by a shallow trench isolation (STI) process, a contact hole manufactured by a self-aligned contact (SAC) technique, a cylinder type capacitor, and a dielectric layer having a Ta
2
O
5
structure.
However, DRAM devices in which the above integration schemes are adopted may encounter the following problems. First, in the case of using a SAC process and a cylinder type capacitor, it is difficult to secure an appropriate process margin, and stability of the process may be degraded. In particular, a cylinder type capacitor adopted in order to improve the capacitance of DRAM devices can suffer from a bridge defect between adjacent bits due to the narrow intervals between nodes of each cylinder type capacitor. Second, a wet strip process for removing a thick interlayer dielectric layer such as an oxide layer required for forming a cylinder type capacitor causes many defects and further complicates fabrication. Thirdly, the step difference between core and cell areas caused by the use of a cylinder type capacitor, requires a thick insulating layer for planarization. Thus, when a metal contact is formed on a core area, there are difficulties encountered in a process of filling the metal contact hole with a conductive material, as well as in forming a metal contact hole in the thick interlayer dielectric layer for planarization.
SUMMARY OF THE INVENTION
The present invention is therefore directed to a semiconductor memory device and fabricating method thereof that substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
To solve the above problems, it is an objective of the present invention to provide a method of fabricating a semiconductor memory device, which is capable of securing a process margin between a bit line pattern and a buried contact hole, preventing the occurrence of a bridge defect between nodes when forming a cylinder type capacitor, suppressing the occurrence of particles, simplifying the fabrication process, and appropriately forming a deep-structured metal contact on a core area.
It is another objective of the present invention to provide a semiconductor memory device using the above fabricating method.
Accordingly, to solve the above objectives, the present invention provides a method of manufacturing a semiconductor memory device including a core area and a cell area. According to the method, first, a gate pattern having capping layers is formed on a semiconductor substrate on which an isolation layer has been formed. Then, a first interlayer dielectric layer is formed on the semiconductor substrate and the gate pattern, and is then patterned to form a direct contact pad and a buried contact pad. A second interlayer dielectric layer is formed on this structure and then a bit line pattern having capping layers is formed in the cell area. A third interlayer dielectric layer is then formed thereon, a buried contact hole connected to the buried contact pad is formed in the cell area by a self aligned contact process, and a buried contact plug for filling the buried contact hole is formed. An etching stopper is then formed on the structure, a first metal contact hole is formed in the core area, and a first metal plug for filling the first metal contact hole is formed. A fourth interlayer dielectric layer is formed on the etching stopper and then patterned to form a fourth interlayer dielectric pattern having a groove which exposes the buried contact plug in the cell area and which exposes the surface of the third interlayer dielectric layer in the core area. A polysilicon layer for a lower electrode is stacked along a step difference of the surface of the fourth interlayer dielectric pattern, and then is selectively removed. A dielectric layer is formed on the polysilicon layer for a lower electrode, and an upper electrode pattern is then formed on the structure so that an upper electrode layer in the core area and an upper electrode layer in the cell area may be connected together. A fifth interlayer dielectric layer is formed on the structure and then a contact hole for wiring that exposes the upper electrode layer in the groove in the core area and a second metal contact hole that exposes the first metal plug are formed. Finally, a contact plug for wiring that fills the contact hole for wiring and a second metal plug that fills the second metal contact hole are formed.
The present invention also provides a method of manufacturing a semiconductor memory device including a core area and a cell area according to another aspect of the present invention. According to the method, first, a gate pattern including capping layers is formed on a semiconductor substrate on which an isolation separation layer has been formed. A first interlayer dielectric layer is formed on the semiconductor substrate and the gate pattern, and is then patterned to form a direct contact pad and a buried contact pad. A second interlayer dielectric layer is formed on this structure, and a bit line pattern having capping layers is formed in the cell area. A third interlayer dielectric layer is then formed thereon, a buried contact hole connected to the buried contact pad is formed by a self aligned contact process in the cell area, and a buried contact plug for filling the buried contact hole is formed. An etching stopper is then formed on the structure, a first metal contact hole is formed in the core area, and a first metal plug for filling the first metal contact hole is formed. A fourth interlayer dielectric pattern which overlies the entire surface of the core area is then formed to include a concave opening that exposes the buried contact plug in the cell area. A polysilicon layer for a lower electrode is stacked along a step difference of the surface of the fourth interlayer dielectric pattern in the cell area, and is then selectively removed. A dielectric layer is formed on the polysilicon layer for a lower electrode. An upper electrode pattern which is connected together in the cell area of the semiconductor substrate and extended to a portion of the core area is formed. A fifth interlayer dielectric layer is formed on the structure, and then a contact hole for wiring that exposes a portion of the upper electrode pattern extended to the core area and a second metal contact hole that exposes the first metal plug are formed. Finally, a contact plug for wiring that fills the contact hole for wiring and a second metal plug that fills the second metal contact hole are formed.
The isolation layer may be formed by a shallow trench isolation process, and the bit line pattern may be formed by sequentially stacking a titanium layer, a barrier layer, and a tungsten layer. The gate pattern and the bit line pattern further may include capping layers composed of insulating layers on top of the gate pattern and the bit line pattern and spacers along the sidewalls thereof. The capping layers may be formed of a nitride layer.
The etching stopper may be formed of a nitride layer. After formin

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