Semiconductor memory device and electronic instrument using...

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S154000, C365S191000

Reexamination Certificate

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06901016

ABSTRACT:
A semiconductor memory device has a first precharge transistor connecting a potential supply line to one end of a bit line when the bit line is precharged and a second precharge transistor connecting the potential supply line to the other end of the bit line when the bit line is precharged. To a gate of the first precharge transistor is inputted a first precharge signal, and to a gate of the second precharge transistor is inputted a second precharge signal generated based on a chip-select signal and the first precharge signal. The second precharge transistor is brought into a cut-off state during a standby state in which a memory cell corresponding to the second precharge transistor does not read nor write data but holds date.

REFERENCES:
patent: 6018488 (2000-01-01), Mishima et al.
patent: 6181640 (2001-01-01), Kang
patent: 6434065 (2002-08-01), Kobayashi et al.
patent: 6452862 (2002-09-01), Tomotani
patent: 6594192 (2003-07-01), McClure

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