Semiconductor memory device and data read method thereof

Details Semiconductor memory device and data read method thereof Semiconductor memory device and data read method thereof

2002-05-13

2003-03-04

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S189050, C365S208000

Reexamination Certificate

active

06529432

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and data read method thereof which can stably output a data read from a memory cell array.
2. Description of Related Art
A conventional semiconductor memory device transmits data read from a memory cell array to common data I/O lines, and outputs the data transmitted to the common data I/O lines via a current-voltage converter, a differential amplifier (or latch), a data output buffer, and a data output driver.
In greater detail, the differential amplifier is arranged at an output stage of the current-voltage converter to amplify output data of the current-voltage converter and to transmit it to the data output buffer. Alternatively, a latch latches output data of the current-voltage converter and transmits it to the data output buffer.
FIG. 1
is a block diagram illustrating a conventional semiconductor memory device. The semiconductor memory device of
FIG. 1
includes a memory cell array
10
, current-voltage converters
20
-
1
to
20
-n, differential amplifiers
22
-
1
to
22
-n, data output buffers
24
-
1
to
24
-n, and data output drivers
26
-
1
to
26
-n.
In particular, in
FIG. 1
, IVC denotes the current-voltage converters, DA denotes the differential amplifiers, DOB denotes the data output buffers, and DOD denotes the data output drivers. LIO11/B to LIO1n/B, . . . , LIOm1/B to LIOmn/B denote local data I/O line pairs, and MIO1/B to MIOn/B denote main data I/O line pairs.
Functions of the components of
FIG. 1
are described focusing on a read operation. Data stored in the memory cell array
10
is transferred to the local data I/O line pairs LIO11/B to LIO1n/B, . . . , LIOm1/B to LIOmn/B and to the main data I/O data line pairs MIO1/B to MIOn/B, in sequence. The current-voltage converters
20
-
1
to
20
-n convert a current difference of the data pairs transferred to the main data I/O line pairs MIO1/B to MIOn/B, respectively, into a voltage difference to generate data X. The data output buffers
24
-
1
to
24
-n buffer the data Z output from the differential amplifiers
22
-
1
to
22
-n, respectively. The data output drivers
26
-
1
to
26
-n drive the data output from the data output buffers
24
-
1
to
24
-n to output data D
1
to Dn, respectively.
FIGS. 2A
to
2
C are timing diagrams illustrating operation of the current-voltage converter and the differential amplifier.
FIG. 2A
shows the timing diagram during normal operation,
FIG. 2B
shows the timing diagram during a high-frequency operation, and
FIG. 2C
shows the timing diagram according to a process variation.
In
FIGS. 2A
to
2
C, CLK denotes a clock signal, CMD denotes a command signal, and a hatched portion denotes an invalid data period.
Referring to
FIG. 2A
, data CSA
1
to CSA
4
are output from the current-voltage converters
20
-
1
to
20
-n in sequence. When a signal Y is input so as to enable the differential amplifiers
22
-
1
to
22
-n, the differential amplifiers
22
-
1
to
22
-n sequentially receive the data CSAL to CSA
4
and sequentially generate the data DO
1
to DO
4
in response to the signal Y. Period “t
1
” represents a time period from a time point that the clock signal CLK is generated when the read command is applied to a time point that the first data CSAL begins to be output through the current-voltage converters
20
-
1
to
20
-n. Period “t
2
” represents a time period from a time point that the clock signal CLK is generated when the read command is applied to a time point that the signal Y is generated. A time period “t
3
” represents an enable period of the signal Y.
Referring to
FIG. 2B
, a cycle that the clock signal CLK is generated becomes faster, and the data CSA
1
to CSA
4
are sequentially output from the current-voltage converters
20
-
1
to
20
-n in response to the clock signal CLK. The differential amplifiers
22
-
1
to
22
-n receive the data CSA
1
to CSA
4
and generate data DO
1
to DO
4
in response to the signal Y. At this point, when the data CSA
2
is input to the differential amplifiers
22
-
1
to
22
-n during the enable period t
3
of the signal Y, the differential amplifiers
22
-
1
to
22
-n output not the data DO
1
but the next data DO
2
. This is because when the data is transited during the enable period t
3
of the differential amplifiers
22
-
1
to
22
-n, the output data of the differential amplifiers
22
-
1
to
22
-n is changed. Accordingly, since the data DO
1
cannot be output in case of
FIG. 2B
, a data read error occurs. That is, in
FIG. 2B
, the data DO
2
to DO
4
are cut partially, but the data DO
2
to DO
4
are connected to be output by the data output buffers.
Referring to
FIG. 2C
, due to a process variation, the data CSA
1
to CSA
4
output from the current-voltage converters
20
-
1
to
20
-n are delayed by a time period t
4
. Even though the data CSA
1
to CSA
4
are delayed by the time period t
4
, when the data CSA
1
to CSA
4
are input within the enable period t
3
of the signal Y, the differential amplifiers
22
-
1
to
22
-n can output the data DO
1
to DO
4
stably. In
FIG. 2C
, the data DO
1
to DO
4
are cut partially, but the data DO
1
to DO
4
are connected to be output by the data output buffers. Therefore, the data read error does not occur.
When a data read path of the semiconductor memory device is configured by the current-voltage converter and the differential amplifier, a data read error occurs during the high-frequency operation but the data read error resulting from the process variation does not occur.
FIG. 3
is a block diagram illustrating a configuration of a data read path of another conventional semiconductor memory device. The semiconductor memory device of
FIG. 3
includes a memory cell array
10
, current-voltage converters
20
-
1
to
20
-n, latches
28
-
1
to
28
-n, data output buffers
24
-
1
to
24
-n, and data output drivers
26
-
1
to
26
-n.
In
FIG. 3
, LA denotes the latch. Like references of
FIGS. 1 and 3
denote like parts. The latch LA latches and outputs output data of the current-voltage converters
20
-
1
to
20
-n in response to the signal Y. The remaining components of
FIG. 3
except the latch LA can be understood with reference to the description of
FIG. 1
, and thus their description is omitted to avoid a redundancy.
FIGS. 4A
to
4
C are timing diagrams illustrating operation of the current-voltage converter and the latch.
FIG. 4A
shows the timing diagram during normal operation,
FIG. 4B
shows the timing diagram during a high-frequency operation, and
FIG. 4C
shows the timing diagram according to a process variation.
In
FIGS. 4A
to
4
C, CLK denotes a clock signal, CMD denotes a command signal, and a hatched portion denotes an invalid data period.
Referring to
FIG. 4A
, data CSA
1
to CSA
4
are output from the current-voltage converters
20
-
1
to
20
-n in sequence. The latches
28
-
1
to
28
-n sequentially receive the data CSA
1
to CSA
4
and sequentially generate the data DO
1
to DO
4
in response to the signal Y. Period “t
1
” represents a time period from a time point that the clock signal CLK is generated when the read command is applied to a time point that the first data CSA
1
begins to be output through the current-voltage converters
20
-
1
to
20
-n. Period “t
2
” represents a time period from a time point that the clock signal CLK is generated when the read command is applied to a time point that the signal Y is generated. Period “t
3
” represents an enable period of the signal Y.
Referring to
FIG. 4B
, a generation cycle of the clock signal CLK becomes faster, and the data CSA
1
to CSA
4
are sequentially output from the current-voltage converters
20
-
1
to
20
-n in response to the clock signal CLK. The latches
28
-
1
to
28
-n receive and latch the data CSA
1
to CSA
4
and generate the data DO
1
to DO
4
at a rising edge of the signal Y.
The latches
28
-
1
to
28
-n maintain the signals latched at a rising edge of the signal Y

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