Semiconductor memory device and data read method of device

Details Semiconductor memory device and data read method of device Semiconductor memory device and data read method of device

1999-07-14

2000-12-12

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518911, 365205, G11C 700

Patent

active

061607428

ABSTRACT:
The semiconductor memory device includes a memory cell array, sense amplifying means for generating a sense output signal pair, and a data output buffer for providing the sense output signal pair. The data output buffer includes a level shifter for generating a first data output signal pair by shifting the level of the sense output signal pair responsive to the output buffer enable signal. A register inverts and latches the first data output signal pair, generating a second data output signal pair. A first transmission and latch means transmits and latches the second data output signal pair generating a third data output signal pair responsive to a first control signal. A second transmission and latch means transmits and latches the second data output signal pair generating a fourth data output signal pair responsive to a second control signal. A first inverter generates a fifth data output signal pair by inverting the third data output signal pair responsive to a first data output control signal. A second inverter generates the fifth data output signal pair by inverting the fourth data output signal pair responsive to a second data output control signal. A first latch generates a sixth data output signal pair by latching the fifth data output signal pair. A logical multiplication means manipulates the sixth data output signal pair responsive to an output enable signal.

REFERENCES:
patent: 5389213 (1995-02-01), Yeon et al.
patent: 5530955 (1996-06-01), Kaneko
patent: 5777938 (1998-07-01), Nakamura et al.
patent: 5877990 (1999-03-01), Kim
patent: 5949721 (1999-09-01), Kwon et al.

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