Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-09-25

2003-01-21

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S221000, C365S230080, C365S233100, C365S239000

Reexamination Certificate

active

06510087

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-296081, filed Sep. 28, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a read register.
2. Description of the Related Art
A circuit configuration of a general high frequency clock synchronous memory is shown in
FIG. 23. A
memory circuit
1
is roughly composed of a memory core section
2
and the other interface I/F circuit.
The I/F circuit comprises: adjacent left and right shift register section
3
at the memory core section
2
; left and right I/O circuits (input/output circuits)
4
disposed between the corresponding external signal lines; a DLL (Delayed Locked Loop) circuit
5
; and a control logic
6
.
The DLL circuit
5
is a circuit that synchronizes with an externally inputted write clock RXCLK, thereby generating a clock “rclk” that controls internal write data, and generating a clock “tclk” that controls internal read data in response to an externally inputted readout clock TXCLK.
In addition, a control logic
6
is a circuit that logically computes a protocol inputted by an external command signal COMMAND, and generates a memory circuit control signal.
The left and right I/O circuits
4
each acquires serial write data DQ <0:7> and DQ <8:15> from an external input/output data line by using an internal write data control clock “rclk”, and outputs internal serial write data eWrite and oWrite to be inputted to the left and right shift register section
3
that consists of a plurality of shift registers.
In addition, by using the internal read data control clock “tclk”, the internal serial read data eRead and oRead are acquired respectively from the left and right shift register section
3
, and serial read data DQ <0:7> and DQ <8:15> are outputted respectively to the external input/output data lines.
The <0:7> and <8:15> used here denotes first-half 8DQ data and latter-half 8DQ data of 16DQ. The characters “e” and “o” assigned to Read and Write denotes even number (even) and odd number (odd) data.
The left and right shift register sections
3
each acquire the internal parallel read data RD <0:7> respectively read out from the memory core section
2
by a control signal during readout operation. Then, these register sections each output the internal parallel write register WD <0:7> respectively by a control signal during write operation, and then, writes it into the memory core section
2
.
In this way, the internal parallel read data RD <0:7> is converted into the internal serial read data “eRead” and “oRead” during readout operation between the left and right I/O circuits
4
each and the memory core section
2
. In addition, the internal serial write data “eWrite” and “oWrite” are converted into the internal parallel write data WD <0:7> during write operation.
The memory core section
2
is composed of a general DRAM circuit that consists of a row decoder, a column decoder, a memory cell array, a sense amplifier, a redundancy phase, and a DQ buffer.
As described above, in a layout configuration of a conventional high frequency clock synchronous memory, parallel read data read out from the memory core section
2
is converted into serial read data by the shift register
3
, and the converted serial read data is delivered to the I/O circuit
4
.
FIG. 24
shows a path from the conversion to the delivery. Serial numbers
0
to
7
and
8
to
15
are assigned to the left and right I/O circuits
4
incorporated in a peripheral circuit section
7
enclosed by dotted line.
In the case where data is written into the memory core section
2
, the serial write data inputted from the I/O circuit
4
is inputted to the shift register section
3
. Then, the inputted write data is written into the memory core section
2
after converted into parallel write data at the shift register section
3
.
In this way, a data flow in write operation can be obtained by reversing the data flow in readout operation. Thus,
FIG. 24
shows a path of read data as an example of readout operation.
In
FIG. 24
, at the memory core sections
2
disposed at the top and bottom of the peripheral circuit section
7
, the 8-bit regions each are assigned to the left memory core section
2
, corresponding to each of the left 8-bit I/O circuits
4
having serial numbers
0
to
7
assigned thereto. Similarly, the 8-bit regions each are assigned to the right memory core section
2
, corresponding to each of the right 8-bit I/O circuits
4
having serial numbers
8
to
15
assigned thereto. Namely, a 16-bit configured high frequency clock synchronous memory is entirely configured.
In this way, as is evident from the memory core section
2
in
FIG. 24
, the 8-bit regions (I/O)
0
(0:7) to (I/O)
15
<0:7> each are assigned to a cell array. When the high frequency clock synchronous memory is active, the above four memory core sections
2
are selected according to a combination of the upper left and lower right or a combination of the lower left and upper right by an address signal.
The read data read out in parallel from the memory core section
2
every 8 bits is converted into each items of 8-bit serial read data at the shift register section
3
. Configurations of the shift register section are shown in
FIGS. 25 and 26
, and a disposition of the shift register section
3
relevant to the memory core section
2
and peripheral circuit section
7
is shown in FIG.
27
.
As shown in
FIGS. 25 and 26
, the write register is composed of: an odd number write register that inputs 4-bit odd number serial write data “oWrite”, and outputs 4-bit odd number parallel data WD <1, 3, 5, 7> ; and an even number write register that inputs 4-bit even number serial write data “eWrite”, and outputs parallel write data WD <0, 2, 4, 6>.
In addition, the read register is composed of: an odd number read register that acquires 4-bit odd number parallel read data RD <1, 3, 5, 7>, and outputs 4-bit odd number parallel read data “oRead” and an even number read register that acquires 4-bit even number parallel read data RD <0, 2, 4, 6>, and outputs 4-bit even number parallel data “eRead”.
In more detail, these write register and read register use both edges of the write and readout control clocks “rclk” and “tclk” to transfer 8-bit data at a clock of 4 cycles.
In addition, the shift register section
3
that consists of a write register and a read register is collected into a block in units of bits that corresponds to each of the bits (I/O)
0
to (I/O)
7
, and a set of shift register sections are configured in a form in which the blocks in units of 8 bits are stacked in a Y direction.
As shown in a pattern layout of
FIG. 27
, such two sets of shift register sections
3
corresponds to 8 bits are disposed at the center in the X direction of a chip. That is, two sets of shift register sections
3
that correspond to 16 I/O circuits
4
are disposed at the center in the X direction.
From the I/O circuits
4
, eight internal serial write data lines for even number data “eWrite” and eight internal serial write data lines for odd number data “oWrite” are corrected respectively to the corresponding 8 write registers for each bit. Thus, a total of 16 internal serial write data are connected to eight write registers through a peripheral circuit.
In addition, eight internal serial read data lines for even number “eRead” and eight internal serial read data lines for odd number data “oRead” are connected respectively to the corresponding eight read registers for each bit. Thus, a total of 16 internal serial read data lines extend to the peripheral circuit section, and are connected to the I/O circuit
4
through the peripheral circuit section.
When the wire resistance from the corresponding read register for each bit to the periphe

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