Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2008-04-22

2008-04-22

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S189080, C365S233100

Reexamination Certificate

active

07362635

ABSTRACT:
A semiconductor memory device includes a control signal generator for combining command signals applied from an external portion to generate a test signal; a set/reset signal generator for receiving a mode setting signal applied from an external portion in response to the test signal and generating a first set/reset signal when the mode setting signal is a signal that designates an individual set/reset; a test logic portion for storing and then outputting the mode setting signal in response to the test signal; a set/reset master signal generator for receiving the first set/reset signal to output a set/reset master signal for commonly controlling a test mode of internal blocks of the semiconductor memory device; and a test control signal generator for combining an output signal of the test logic portion to generate a plurality of control signals and generating the set/reset master signal as a plurality of test control signals in response to the plurality of control signals.

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