Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-09-14

2001-12-18

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230030, C365S063000

Reexamination Certificate

active

06331955

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, more particularly, which can transmit data at a high speed by reducing the signal line loading difference between output lines of a data output control signal generator and the data output buffers at the time of a data read operation.
DESCRIPTION OF THE PRIOR ART
A conventional semiconductor memory device includes a data output control signal generator, data output buffers, and data output drivers on a data read path to read data outputted from memory cells.
The data output control signal generator generates control signals KPIPE and KDATA for controlling the data output buffers. The data output buffers latch and output data in response to the pipeline control signal KPIPE, and latch and output the latched data in response to the clock control signal KDATA. The data output drivers output data from the data output buffers to an external bus.
In a conventional semiconductor memory device, signal line loading of output lines of the data output control signal generator is greater than signal line loading of output lines of the data output buffers. In addition, signal lines from the data output control signal generator to the data output buffers are typically longer than those from the data output buffers to the data output drivers, so that the signal line loading of the output lines of the data output control signal generator is much greater than that of the output lines of the data output buffers.
That is, the signal line loading of the output lines of the data output control signal generator has a large value, and its load becomes much greater as the signal lines from the data output control signal generator to the data output drivers become longer. On the contrary, the signal line loading of the output lines of the data output buffers has a small value, and its load becomes relatively smaller than that of the output lines of the data output control signal generator as the signal lines from the data output buffer to the data output driver become shorter.
Accordingly, in the conventional semiconductor memory device, the signal line loading difference between output lines of the data output control signal generator and those of the data output buffers becomes so large that the speed at which the memory device can transmit data is limited.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device which can transmit data at a higher speed by reducing the difference of signal line loading according to the length of the signal lines in order to solve the above-mentioned problem of the prior art.
To accomplish the above object of the present invention, the semiconductor memory device includes a plurality of memory cell array blocks; a plurality of sense amplifiers which are respectively coupled to the plurality of memory cell array blocks for amplifying and outputting data outputted from each of the plurality of memory cell array blocks; a plurality of data output buffers for buffering and outputting the data outputted from the plurality of sense amplifiers in response to control signals; a plurality of data output drivers for driving the data outputted from the plurality of data output buffers; and a data output control signal generator for generating the control signals, wherein the plurality of data output buffers are disposed adjacent the data output control signal generator.
Also, to accomplish the above object of the present invention, the semiconductor memory device includes a plurality of memory cell array blocks, a plurality of data output buffers for buffering and outputting data outputted from each of the plurality of memory cell array blocks in response to control signals; a plurality of data output drivers for driving the data outputted from the plurality of data output buffers; and a data output control signal generator for generating the control signals, wherein the plurality of data output buffers are disposed adjacent the data output control signal generator.
The detailed description of the preferred embodiments according to the present invention will be apparent with reference to the attached drawings.


REFERENCES:
patent: 4050061 (1977-09-01), Kitagawa
patent: 5621695 (1997-04-01), Tran
patent: 6041013 (2000-03-01), Kohno

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