Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1985-11-27

1987-09-15

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365185, G11C 700

Patent

active

046944290

ABSTRACT:
There is disclosed a semiconductor memory device comprising a memory cell connected to a bit line, and a clamp circuit comprising a load MOS transistor connected between a power source voltage and the bit line, for clamping the power source voltage and applying the clamped voltage to the bit line. The semiconductor memory device further comprises a bypass circuit connected between the bit line and a reference voltage, for bypassing from the bit line to the reference voltage an electric current the amount of which is substantially equal to that of a weak inversion current of the load MOS transistor flowing into said bit line.

REFERENCES:
patent: 4156941 (1979-05-01), Homma et al.
patent: 4223394 (1980-09-01), Pathak et al.
patent: 4347586 (1982-08-01), Natsui
patent: 4488263 (1984-12-01), Herndon et al.

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