Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Precharge

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36518911, G11C 700

Patent

active

060943920

ABSTRACT:
A plurality of bit line pairs are provided in a semiconductor memory device. A plurality of memory cells are connected to the first bit line pairs. Also, in the semiconductor memory device, there are provided a first sense amplifier, a second bit line pair and a second sense amplifier. The first sense amplifier reads and amplifies a potential difference between the first bit line pair. A signal output from the first sense amplifier is transmitted to the second bit line pair. The second sense amplifier amplifies a potential difference between the second bit line pair. A precharge circuit is built in the second sense amplifier. The first bit line pairs are precharged by the precharge circuit.

REFERENCES:
patent: 5675529 (1997-10-01), Poole
patent: 5796665 (1998-08-01), Ternullo, Jr. et al.
patent: 5930197 (1999-07-01), Ishibashi et al.
patent: 6018486 (2000-06-01), Ferrant

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