Semiconductor memory and method of controlling data therefrom

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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365 63, G11C 700

Patent

active

061669644

ABSTRACT:
A semiconductor memory, such as a multibit DRAM, has a multiple cell array banks, each having multiple cell arrays. Rows of sense amplifiers are located near each of the cell arrays and extend in a first direction. Multiple rows of transfer switches, also extending in the first direction, are located adjacent to each of the cell array banks. A first data bus, which extends in a second direction which is perpendicular to the first direction, connects the sense amplifiers with the transfer switches. Multiple data buffer rows extend in the first direction near the transfer switches. A second data bus, extending in the first direction, connects the transfer switches with the data buffers. A layout pitch is defined by a spacing between adjacent lines of the first data bus. The transfer switches are placed in accordance with the defined layout pitch and the data buffers are placed according to a layout pitch determined by multiplying the defined layout pitch by the number of cell array banks.

REFERENCES:
patent: 5764562 (1998-06-01), Hamamoto
patent: 5847985 (1998-12-01), Mitani et al.
patent: 6084817 (2000-07-01), Toda

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