Semiconductor LSI circuit with scan circuit, scan circuit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Reexamination Certificate

active

10981986

ABSTRACT:
A semiconductor LSI circuit provided with a scan circuit includes: to-be-tested combinational logic circuits; scan circuits adjacent to and disposed alternately with the combinational logic circuits; scan elements, which form the scan circuits; a first selector inserted in a first scan circuit scan and connects a first group of scan elements and a second group of scan elements; a second selector inserted in a second scan circuits and connects a third group of scan elements and a fourth group of scan elements; a first route provided in the first group of scan elements and extending from a scanning output terminal of a scan element; and a second route provided in a third group of scan elements and extending from the scanning output terminal of a scan element. The first selector selects either the first route or the second route.

REFERENCES:
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patent: 2003/0115522 (2003-06-01), Nadeau-Dostie et al.
patent: 2003/0149925 (2003-08-01), Angelotti et al.
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patent: 2003-150658 (2003-05-01), None
Official Action issued on May 23, 2006 (Japanese and English translations) regarding the counterpart Japanese Patent Application No. 2003-382554.

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