Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-03-06
2007-03-06
Tu, Christine T. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
10981986
ABSTRACT:
A semiconductor LSI circuit provided with a scan circuit includes: to-be-tested combinational logic circuits; scan circuits adjacent to and disposed alternately with the combinational logic circuits; scan elements, which form the scan circuits; a first selector inserted in a first scan circuit scan and connects a first group of scan elements and a second group of scan elements; a second selector inserted in a second scan circuits and connects a third group of scan elements and a fourth group of scan elements; a first route provided in the first group of scan elements and extending from a scanning output terminal of a scan element; and a second route provided in a third group of scan elements and extending from the scanning output terminal of a scan element. The first selector selects either the first route or the second route.
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Official Action issued on May 23, 2006 (Japanese and English translations) regarding the counterpart Japanese Patent Application No. 2003-382554.
DLA Piper (US) LLP
Kabushiki Kaisha Toshiba
Tu Christine T.
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